Patents Represented by Attorney Williams, Morgan and Amerson

Find this attorney in the Justia Lawyer Directory

  • Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment
    Patent number: 8211795
    Abstract: A new technique is disclosed in which a barrier/cap layer for a copper based metal line is formed by using a thermal-chemical treatment based on hydrogen with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma based deposition of silicon based dielectric barrier material. The thermal-chemical cleaning process is performed in the absence of any plasma ambient.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: July 3, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joerg Hohage, Volker Kahlert, Hartmut Ruelke, Ulrich Mayer
  • Application-specific group listing
    Patent number: 8209376
    Abstract: A method, apparatus, and system for providing active contents between applications activated by a plurality of computer systems are provided. A list of one or more remote users is created. A determination is made whether a first application and a second application are being executed by the at least one or more remote users. The list is updated in response to determining a change in a status of the second application being executed by the one or more remote users using at least one communications feature associated with the first application.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: June 26, 2012
    Assignee: Apple Inc.
    Inventor: Michael Stochosky
  • Method of providing transcoding during voice-over-internet protocol handoff
    Patent number: 8204022
    Abstract: The present invention provides a method for supporting handoffs of a first mobile unit in a wireless communication system that supports multiple vocoder technologies. The method includes allocating, prior to completion of a handoff of the first mobile unit, a transcoder function to the first mobile unit. The method also includes detecting a change in a format of at least one packet received from the first mobile unit. The change indicates that the vocoder technology used by the first mobile unit to form packets has changed. The method also includes transcoding packets in response to detecting the change in the format.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: June 19, 2012
    Assignee: Alcatel Lucent
    Inventors: Harold Aaron Lassers, Chung-Zin Liu
  • Transistor with an embedded strain-inducing material having a gradually shaped configuration
    Patent number: 8202777
    Abstract: In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 19, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephan Kronholz, Vassilios Papageorgiou, Gunda Beernink
  • Apparatus and method for separating solids from a solids laden liquid
    Patent number: 8201693
    Abstract: An apparatus and method for separating solids from a solids laden drilling mud (14), the method comprising the steps of introducing solids laden drilling mud to a first side of a screen (13), the drilling mud passing through the screen (13) and screened drilling mud located the other side of the screen (13) characterized in that an oscillating tray (18) is located in the drilling mud and spaced from the screen, the oscillating tray imparting motion to the drilling mud to facilitate screening of said solids laden drilling mud in the screen (13).
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: June 19, 2012
    Assignee: National Oilwell Varco, L.P.
    Inventor: Helge Sorensen Jan
  • Hydrocyclones for treating drilling fluid
    Patent number: 8202415
    Abstract: Methods and systems are disclosed for treating a drilling fluid mixture including feeding the drilling fluid mixture to a hydrocyclone (or hydrocyclones) with a flow-volume-adjustable inlet for controlling flow of the drilling fluid mixture into the hydrocyclone(s). This abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 C.F.R. 1.72(b).
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: June 19, 2012
    Assignee: National Oilwell Varco, L.P.
    Inventor: Thomas Robert Larson
  • Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process
    Patent number: 8198190
    Abstract: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: June 12, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Robert Seidel, Juergen Boemmels, Thomas Foltyn
  • Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization
    Patent number: 8198192
    Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: June 12, 2012
    Assignee: GlobalFoundries Inc.
    Inventors: Richard Carter, Martin Trentzsch, Sven Beyer, Rohit Pal
  • Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer
    Patent number: 8198147
    Abstract: In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: June 12, 2012
    Assignee: GlobalFoundries, Inc.
    Inventors: Frank Feustel, Kai Frohberg, Thomas Werner
  • Using high-k dielectrics as highly selective etch stop materials in semiconductor devices
    Patent number: 8198166
    Abstract: A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: June 12, 2012
    Assignee: GlobalFoundries, Inc.
    Inventors: Thorsten Kammler, Ralf Richter, Markus Lenski, Gunter Grasshoff
  • Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials
    Patent number: 8198152
    Abstract: In sophisticated semiconductor devices, a replacement gate approach may be applied, in which a channel semiconductor material may be provided through the gate opening prior to forming the gate dielectric material and the electrode metal. In this manner, specific channel materials may be provided in a late manufacturing stage for different transistor types, thereby providing superior transistor performance and superior flexibility in adjusting the electronic characteristics of the transistors.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: June 12, 2012
    Assignee: GlobalFoundries, Inc.
    Inventors: Sven Beyer, Jan Hoentschel, Thilo Scheiper, Uwe Griebenow
  • Stress transfer enhancement in transistors by a late gate re-crystallization
    Patent number: 8198633
    Abstract: A gate electrode structure of a transistor may be formed so as to exhibit a high crystalline quality at the interface formed with a gate dielectric material, while upper portions of the gate electrode may have an inferior crystalline quality. In a later manufacturing stage after implementing one or more strain-inducing mechanisms, the gate electrode may be re-crystallized, thereby providing increased stress transfer efficiency, which in turn results in an enhanced transistor performance.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: June 12, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel
  • Method of providing route update messages and providing messages to access terminals
    Patent number: 8195157
    Abstract: The present invention provides a method including providing at least one route update message based upon at least one sector list associated with an access terminal. The sector lists are formed based on information collected by the access terminal.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: June 5, 2012
    Assignee: Alcatel Lucent
    Inventors: David Albert Rossetti, Yang Yang, Sigen Ye, Jialin Zou
  • Semiconductor device comprising a silicon/germanium resistor
    Patent number: 8193066
    Abstract: In integrated circuits, resistors may be formed on the basis of a silicon/germanium material, thereby providing a reduced specific resistance which may allow reduced dimensions of the resistor elements. Furthermore, a reduced dopant concentration may be used which may allow an increased process window for adjusting resistance values while also reducing overall cycle times.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: June 5, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Andreas Kurz, Roman Boschke, Christoph Schwan, John Morgan
  • Local silicidation of via bottoms in metallization systems of semiconductor devices
    Patent number: 8193086
    Abstract: Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 5, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tobias Letz, Frank Feustel
  • Determining die performance by incorporating neighboring die performance metrics
    Patent number: 8190391
    Abstract: A method includes receiving a first set of parameters associated with a plurality of die. A first die performance metric associated with a selected die is determined based on the first set of parameters. At least one neighborhood die performance metric associated with a set comprised of a plurality of die that neighbor the selected die is determined based on the first set of parameters. A second die performance metric is determined for the selected die based on the first die performance metric and the neighborhood die performance metric.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 29, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Daniel Kadosh, Gregory A. Cherry, Carl I. Bowen, Luis De La Fuente, Rajesh Vijayaraghavan
  • Drive current adjustment for transistors by local gate engineering
    Patent number: 8188871
    Abstract: In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: May 29, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manfred Horstmann, Patrick Press, Karsten Wieczorek, Kerstin Ruttloff
  • Method and apparatus for predicting device electrical parameters during fabrication
    Patent number: 8185230
    Abstract: A method includes providing a set of initial characteristic values associated with the semiconductor device. A first fabrication process is performed on the semiconductor device. Fabrication data associated with the first fabrication process is collected. At least one of the initial characteristic values is replaced with the fabrication data collected for the first fabrication process to generate a first modified set of characteristic values. A first value for at least one electrical characteristic of the semiconductor device is predicted based on the modified set of characteristic values. A system includes a first process tool, a first data collection unit, and a prediction unit. The first process tool is configured to perform a first fabrication process on the semiconductor device. The first data collection unit is configured to collect fabrication data associated with the first fabrication process.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: May 22, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael L. Miller, Christopher A. Bode
  • Multiple gate transistor having fins with a length defined by the gate electrode
    Patent number: 8183101
    Abstract: The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: May 22, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Mulfinger, Andy Wei, Jan Hoentschel, Andrew Waite
  • Method and system for scheduling a stream of products in a manufacturing environment by using process-specific WIP limits
    Patent number: 8185226
    Abstract: By defining a section-related WIP limit or a throughput-related WIP limit, an efficient “look ahead” characteristic may be established to efficiently control the WIP in a complex manufacturing environment, such as a semiconductor facility. The respective critical WIP values may enable efficient reduction of priority of products moving towards an increased WIP queue, thereby reducing or substantially avoiding the release of products that are expected to run into the WIP queue. In this way, the efficiency of shared tools may be increased, since process capacity no longer required for the processing products running into WIP queues may be allocated for other operations.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: May 22, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Joerg Weigang, Robert Ringel, Steffen Kalisch, Thomas Quarg