Patents Represented by Attorney Williams, Morgan and Amerson
  • Patent number: 8163594
    Abstract: In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: April 24, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Seidel, Frank Feustel, Ralf Richter
  • Patent number: 8158486
    Abstract: By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative embodiments, the different anneal temperature may be achieved on the basis of an appropriate mask layer, which may provide a patterned optical response for a lamp-based or laser-based anneal process. Consequently, the intrinsic stress of isolation trenches may be specifically adapted to the requirements of circuit elements, such as N-channel transistors and P-channel transistors.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: April 17, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Van Bentum, Klaus Hempel, Roland Stejskal
  • Patent number: 8158482
    Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: April 17, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
  • Patent number: 8158065
    Abstract: By providing a tool internal sensor device in a process tool in a semiconductor facility, metal contamination may be monitored in situ, thereby avoiding or at least significantly reducing the requirement for sophisticated sample preparation techniques, such as vapor phase decomposition tests in combination with subsequent analysis procedures. Thus, a full time inspection of process tools may be accomplished.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: April 17, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Martin Trentzsch, Stephan Kronholz, Rolf Stephan
  • Patent number: 8160240
    Abstract: A communication system includes transmit and receive paths, a balancing filter, a noise generator, a detector, and an interface. The transmit path is operable to generate data for communication on a communication network. The receive path is operable to receive data from the communication network. The balancing filter is coupled between the transmit path and the receive path. The noise generator is operable to inject a noise signal on the receive path. The detector is operable to measure reflected power in the transmit path associated with the noise signal. The interface is operable to receive a plurality of sets of coefficients for configuring the balancing filter, wherein the detector is operable to measure the reflected power for each of the sets of coefficients.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: April 17, 2012
    Assignee: Microsemi Semiconductor (U.S.) Inc.
    Inventor: Edward Warren Cox
  • Patent number: 8153524
    Abstract: During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: April 10, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Oliver Aubel, Joerg Hohage, Frank Feustel, Axel Preusse
  • Patent number: 8155770
    Abstract: Metrology data associated with a plurality of workpieces processed at a selected operation in the process flow including a plurality of operations is retrieved. A processing context associated with each of the workpieces is determined. The processing context identifies at least one previous tool used to perform an operation on the associated workpiece prior to the selected operation. A plurality of performance metrics is determined for a plurality of tools capable of performing the selected operation based on the metrology data. Each performance metric is associated with a particular tool and a particular processing context. A set of the performance metrics is identified for the plurality of tools having a processing context matching a processing context of a selected workpiece awaiting performance of the selected operation. The selected workpiece is dispatched for processing in a selected one of the plurality of tools based on the set of performance metrics.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: April 10, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert Barlovic, Uwe Schulze, Jan Raebiger, Joerg Weigang, Jens Busch, Rolf Seltmann
  • Patent number: 8154084
    Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: April 10, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Vassilios Papageorgiou, Belinda Hannon
  • Patent number: 8152595
    Abstract: In a polishing process, the characteristics of the removal process may be monitored at different lateral positions to identify the clearance of the various device regions with a high degree of reliability. Consequently, upon forming sophisticated metallization structures, undue over-polishing may be avoided while at the same time providing reduced leakage currents due to enhanced material removal.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: April 10, 2012
    Assignee: Advanced Micro Devices Inc.
    Inventors: Mike Schlicker, Gerd Marxsen
  • Patent number: 8150412
    Abstract: The present invention provides a method of interference mitigation in a wireless communication system. The method that may include reducing transmission power associated with at least one first channel provided by at least one first base station associated with at least one corresponding first coverage area adjacent a second coverage area associated with a second base station concurrently with maintaining at least one transmission power associated with the second base station(s). The method may also include increasing the transmission power associated with the first channel(s) provided by the first base station(s) concurrently with reducing at least one transmission power associated with at least one first channel provided by the second base station(s).
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: April 3, 2012
    Assignee: Alcatel Lucent
    Inventors: Fang-Chen Cheng, Lei Song, Shupeng Li
  • Patent number: 8147670
    Abstract: The present disclosure generally addresses the problem of controlling a plating profile in multi-step recipes and addresses, in particular, the problem of compensating for variations of the plating tool state to stabilize the plating results. The compensation is done by adjustments of corrections factors for currents of a plating tool in a multi-anode configuration. The described method enables control of recipes with different current ratios in each recipe step and models different deposition sensitivities in each recipe step. Generally, the method of the present disclosure requires a measurement step, where the tool state is determined, and a data processing step, where the correction factors are set based on models describing the plating process and the tool state.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: April 3, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sylvia Boehlmann, Dirk Wollstein, Susanne Wehner
  • Patent number: 8149684
    Abstract: The code space associated with the communication system is divided into at least two subspaces where each subspace is assigned to a different mode of operation. In one mode, such as a voice mode, each user is given full time access to a portion of the subspace associated with that mode of operation. In a second mode, such as a data mode, each user uses the entire subspace associated with that mode on a time shared basis.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: April 3, 2012
    Assignee: Alcatel Lucent
    Inventor: Mehmet Oguz Sunay
  • Patent number: 8149384
    Abstract: A method for monitoring a photolithography system includes defining a model of the photolithography system for modeling top and bottom critical dimension data associated with features formed by the photolithography system as a function of dose and focus. A library of model inversions is generated for different combinations of top and bottom critical dimension values. Each entry in the library specifies a dose value and a focus value associated with a particular combination of top and bottom critical dimension values. A top critical dimension measurement and a bottom critical dimension measurement of a feature formed by the photolithography system using a commanded dose parameter and a commanded focus parameter are received. The library is accessed using the top and bottom critical dimension measurements to generate values for a received dose parameter and the received focus parameter.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: April 3, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Siddharth Chauhan, Kevin R. Lensing, James Broc Stirton
  • Patent number: 8143132
    Abstract: In sophisticated semiconductor devices, the threshold voltage adjustment of high-k metal gate electrode structures may be accomplished by a work function metal species provided in an early manufacturing stage. For this purpose, a protective sidewall spacer structure is provided, which is, in combination with a dielectric cap material, also used as an efficient implantation mask during the implantation of extension and halo regions, thereby increasing the ion blocking capability of the complex gate electrode structure substantially without affecting the sensitive gate materials.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: March 27, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Jan Hoentschel, Sven Beyer, Thilo Scheiper
  • Patent number: 8143133
    Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: March 27, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Thomas Feudel, Ralf Illgen
  • Patent number: 8138038
    Abstract: In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape after the deposition of a work function adjusting species on the basis of a polishing process, wherein a sacrificial material may protect the sensitive materials in the gate opening.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: March 20, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Gerd Marxsen, Katja Steffen
  • Patent number: 8138571
    Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: March 20, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Christoph Schwan, Joe Bloomquist, Peter Javorka, Manfred Horstmann, Sven Beyer, Markus Forsberg, Frank Wirbeleit, Karla Romero
  • Patent number: 8138050
    Abstract: Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: March 20, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vassilios Papageorgiou, Jan Hoentschel, Robert Mulfinger, Casey Scott
  • Patent number: 8140159
    Abstract: A method, system, and apparatus for implementing a safe mode operation of an implantable medical system using impedance adjustment(s) are provided. A first impedance is provided to a lead. An indication of a possibility of a coupled energy is received. Based upon said indication, a second impedance associated with the lead to reduce the coupled energy is provided.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: March 20, 2012
    Assignee: Cyberonics, Inc.
    Inventors: Dana Michael Inman, Randolph K. Armstrong, Scott A. Armstrong
  • Patent number: 8137818
    Abstract: Herein disclosed is a composition containing from about 5 weight parts to about 50 weight parts of a branched polylactic acid; from about 50 weight parts to about 95 weight parts of water; and from about 0.1 weight parts to about 1 weight part of a first surfactant. The composition can be coated onto a substrate containing paper or paperboard and having a first surface and a second surface, to form a paper product having oil, grease, and moisture resistance.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: March 20, 2012
    Assignee: Tate & Lyle Ingredients Americas LLC
    Inventors: Michael D. Harrison, Geoffrey A. R. Nobes, Penelope A. Patton, Shiji Shen, Henk Westerhof