Abstract: At a transmit site of an inverse multiplexing system, an input demultiplexer demultiplexes high bandwidth serial communication signals (e.g., fractional T3 rate signals) into communication signal packets for transmission over reduced bandwidth serial communication (e.g. T1) channels. A multiplexer for each channel combines successive packets of demultiplexed signals with bits of multibit packet reassembly control words that identify the channel and the order in which communication signal packets have been demultiplexed, to produce successive frames for transmission over the channel. At a receiver site the control words are extracted from the frames of data and analyzed to control reassembly of the serial data packets into their original order.

Abstract: A bidirectional serial TDM backplane—UTOPIA interface contains an ATM cell boundary location and transmit flow control mechanism, to provide for the efficient capture and storage of ATM cells from a serial TDM channel. Once stored in a transmit buffer, individual ATM cells are controllably read out for application to a downstream UTOPIA interface. In the upstream direction from the UTOPIA bus toward the serial TDM backplane, ATM cells are stored in a multi-cell receive buffer, so that they may be serialized for application to the TDM backplane. In the absence of ATM data cells to transfer, unfilled timeslots are filled with idle cells to maintain the ATM bus active.

Abstract: A back-up channel line card-installed ESF framing mechanism independently sources an FDL signaling channel for the transport of protection switch signaling information, taking advantage of the fact that DSL multiplexer equipment is capable of accepting and processing ESF framed digital data, including embedded FDL-based signaling information. Upon completion of transport of the FDL-based signaling information, the back-up channel is used for data transport in place of a faulty channel.

Abstract: An integrated system concurrently connects voice and data communications devices used by small and medium sized businesses to a network T1 data line terminating at the customer premises. A system chassis includes multiple slots and backplane connectors for removably receiving a bank controller unit (BCU), power service unit (PSU), and one or more different types of smart and dumb voice and data access modules that provide the functional interface to the customer premises equipment. The BCU controls the operation of the system, which can be configured by the customer through an external terminal interface.

Abstract: The inability of an ISDN equipment user to properly configure ISDN terminal equipment, even when provided with correctly assigned switch protocol, SPID and LDN parameters by a telephone service provider, is successfully remedied by a SPID/switch protocol detector. Upon being invoked by the user, the routine proceeds to conduct an iterative search of stored SPID formats associated with different central office switch protocols. SPIDs are assembled in accordance with the iteratively accessed SPID formats and directory number information that has been entered by the user. If an attempt to register a SPID is successful, the routine places a test call. If the test call is successful, the SPID and its associated switch protocol will have been identified, and the terminal equipment may place a call.

Abstract: A repeater-installed fault location mechanism conducts parametric measurements on a segment of wireline to which the repeater is connected, and adjusts taps of an echo cancellation operator in the repeater transceiver equipment, in accordance with the response of the wireline to an electrical stimulus imparted to the wireline segment. Information representative of the echo canceler tap coefficients is then transmitted over an overhead to a processor, to determine fault the location of a fault.

Abstract: A data communication system comprises a forward error correction (FEC) module, a first transceiver, a second transceiver, and logic. The FEC module is configured to receive data and to define FEC code words based on the received data. The first transceiver is coupled to a first communication line, and the second transceiver is coupled to a second communication line. The logic is configured to selectively enable the FEC module to implement a desired FEC scheme based on an estimated error rate associated with the first communication line and an estimated error rate associated with the second communication line.

Abstract: A system for provisioning a network access device based on control settings received from a remote location utilizes logic and memory for storing a set of operational control settings and a set of default control settings for the network access device. The logic is configured to store, in the memory, the operational control settings based on data received from a remote device via a network. The logic is configured to control the network access device based on the operational control settings and to begin controlling the network access device based on the default control settings in lieu of the operational control settings in response to a determination that the network access device is unable to communicate over the network based on the operational control settings, thereby enabling the network access device to be remotely re-provisioned.

Abstract: A test apparatus for telecommunication equipment includes motherboard that executes a resident operation control mechanism, so that the test apparatus exhibits default hardware functionality. However, if a daughtercard has been plugged into the motherboard, the motherboard ignores the default firmware and executes whatever replacement operation control software is provided on the daughtercard—causing the test apparatus to acquire a hardware functionality exclusive of the motherboard default.

Abstract: A cascaded signal processing arrangement processes digitally encoded voice samples transported over a time division multiplex (TDM) communication path for application to a processor-controlled digital communication device, in particular an integrated access device. Processed voice samples are packetized in accordance with an encapsulating protocol and transmitted as a packetized voice output stream to a destination receiver device. The arrangement includes an echo canceller coupled to the TDM communication path and performing echo cancellation processing on the digitally encoded voice samples. The echo cancellation-processed voice sample signals are compressed by a data compression operator and applied to a packet encapsulating host processor via the TDM communication path. This obviates the necessity of the host processor having to use data bus cycles to download processed digitized voice samples.

Abstract: A synthetic impedance telecommunication line driver has no electrical energy-dissipating elements in series with its output, and synthesizes its output impedance in accordance with current fed back from an output current (mirror) sensing circuit. This allows the driver to realize substantially reduced power requirements for driving a telecommunication line, such as, but not limited to a DSX-1 line. The driver includes an operational amplifier having a first polarity input coupled through an input resistor to an input port, to which a signal voltage to applied to an output port is coupled. A second polarity input of the amplifier is coupled to a reference voltage. A feedback resistor is coupled between the amplifier output and its inverting input. An output current-dependent current source, such as a current mirror coupled in circuit with the output node, generates a current as a small fraction k of the output current.

Abstract: A system has a first digital-to-analog (D/A) converter to receive a digital signal and to convert the digital signal into an analog pulse, a second D/A converter to cancel residual energy resulting from a previous pulse if a predetermined sequence of digital data is received, and a third D/A converter to control a falling edge of the analog pulse. Additionally, the system has logic to detect the sequence of digital data and to generate control data for at least one of the D/A converters from the digital data sequence thereby ensuring that the analog signal complies with the specified pulse mask template.

Abstract: A (DS3) network interface unit (NIU) by-pass architecture places the NIU on its own circuit card and exclusive of by-pass switching (and relay) components, which are installed in the equipment shelf, proper, so that physical removal of the NIU card will leave the by-pass circuitry intact. The by-pass circuit responds to an abnormality of the NIU card, such as malfunction or physical removal of the NIU from its card slot, and also to a power supply failure. It also contains an indicator to draw attention to a failed NIU, increasing the likelihood that someone will notice a damaged card.

Abstract: A forward error correction system comprises a forward error correction (FEC) module and a transmission module. The FEC module is configured to define a plurality of FEC code words, and the transmission module is configured to transmit the FEC code words to a remote receiving unit via a plurality of communication connections. The transmission module is further configured to ensure that characters of each of the FEC code words are transmitted across different ones of the communication connections.

Abstract: A dual solid state switch architecture has a plurality of control/monitor ports, selected ones of which are used to control the operation of a pair of power MOSFETs current flow paths through which are coupled to prescribed ones of a plurality of input/output ports that are adapted to be coupled to a circuit path containing a load and either and AC or DC power source therefor. Selected others of the control/monitor ports are used to monitor current delivered to the load. A leakage current by-pass resistor is connected between selected input/output ports, to which a neon tube may be connected for indicating the switching on of an AC source. This resistor serves to provide a bypass path for leakage current through the MOSFETs, so as to prevent the neon tube from being erroneously illuminated, when the MOSFETs have been turned off.

Abstract: A byte boundary information recovery mechanism locates the first bits of respective bytes of an asynchronous transfer mode (ATM)-based serial data stream, used by a frame synchronization mechanism to delineate respective cells of the ATM stream, and thereby enables transceiver equipment to successfully receive and parse ATM traffic. The invention employs a counter offset-based scheme that generates an output signal in potential alignment with the (first bit) boundary of a byte of the data stream, in response to the contents of a counter reaching a prescribed count value. It then iteratively shifts, as necessary, the bit time at which the output signal is produced relative to the counting operation of the counter, until the output signal is aligned with the boundary of a byte of the data stream.

Abstract: The interface apparatus has a connector-receiving unit for receiving a connector that is electrically connected via a conductor to a first device. The connector has a receiving opening corresponding to the conductor. The apparatus further has a port for receiving a cable terminator electrically connected to a second device that is configured to communicate with the network component. Furthermore, the apparatus has a component electrically connected to the port that has a conductive probe movably positioned with respect to the receiving opening corresponding to the conductor of the connector. The component has an actuation component that moves the conductive probe into the receiving opening of the connector when actuated thereby establishing a conductive path between the first device and the second device.

Abstract: An integrated access device is automatically configured to conduct packetized voice and data communications between a customer's voice/data equipment and a digital communications switch. For this purpose, the IAD's communication control processor is programmed to perform an automated analysis of the digital communications link and thereby identify communication interface circuits such as DSLAM and voice gateway units, that have been installed by the service provider. It then automatically configures the communication parameters of the IAD for communication compatibility with the communication interface circuits.

Abstract: Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.

Abstract: A comparator-based switchmode power converter monitors the most negative of the tip and ring line voltages, to control the supply voltage to a SLIC. The voltage applied to the SLIC's power terminals is slightly higher than the sensed voltage for different loop signaling conditions, including loop start, ground start balanced ringing. The switchmode converter includes a comparator coupled to a DC-DC output node downstream of a MOSFET switch installed in a DC supply rail of a source of DC supply voltage, and coupled to a power supply terminal of the SLIC. The comparator is also coupled to a set point node, which is coupled through a voltage offset path to each of tip and ring portions of the telephone line.