Abstract: A regulated power supply interface has a current feedback and voltage level shift circuit that monitors power supply output (load) current and controllably diverts current to a current reference node. A differential amplifier-based, voltage feedback and voltage level shift circuit monitors the load voltage and controllably diverts output current to the current reference node. A current mode setpoint circuit has multiple voltage dropping current paths, through one or more of which a summation of the diverted load currents are programmably directed, to generate a control voltage for controlling the operation of a pulse width modulator unit of the regulated power supply.

Abstract: A voice path direct memory access (DMA)-based packet generation mechanism writes digitally encoded voice samples directly into prescribed subportions of a preallocated portion of random access memory, to avoid interrupting a main processor for the purpose. A pointer to a respective buffer space subportion is presented to a protocol stack, so that one or more overhead bytes for the stored voice samples can be generated and written into adjacent address space of the preallocated portion of random access memory. The contents of the preallocated memory space are then serialized out for transmission to a destination receiver.

Abstract: A search path recovery mechanism for a sequential decoder employs a prescribed self-concatenated “Loeliger” convolutional code, that is either decodable by the sequential decoder for data recovery, or is decodable (although sub-optimally) by a Viterbi decoder as an adjunct to the sequential decoder to improve statistics during path recovery. The Viterbi decoder is incorporated in an alternate decoder which includes metric calculators, that compute branch metrics, that are alternately coupled to the Viterbi decoder, operating at twice the symbol rate. Using estimate bits from the Viterbi decoder, a syndrome former estimates the recovered state and generates an estimate of the validity of the recovered state. Their validity is verified by a path recovery detector, which operates as a zero error detection filter by summing a prescribed number of previous syndrome former outputs.

Abstract: Relatively low cost asymmetric digital subscriber line (ADSL) service and auxiliary POTS service are delivered over extended distances (e.g., at least 20–25 kft), by a hybrid ADSL-SDSL architecture insertable between central office and remote sites of an ADSL system. Central office and remote site transceivers employ trellis coded pulse amplitude modulation and a data rate that conforms with the signal transport capability of an extended distance symmetric DSL (SDSL) loop, while providing a 64K POTS channel. The central office and remote site transceivers controllably insert idle asynchronous transfer mode (ATM) cells in upstream and downstream ADSL channels to compensate for timing differences with ADSL equipment.

Abstract: A digital subscriber loop line card-installed mechanism conducts parametric measurements on the wireline to which the line card is connected, and adjusts taps of an echo cancellation operator in accordance with the response of the wireline to an electrical stimulus imparted to the wireline. The echo canceler tap coefficients are then processed to determine the location of a fault, such as a short circuit, open-circuit and the like, on the wireline. Fault information measurement data is then reported to a supervisory control location, which dispatches the appropriate technician to resolve the cause of the problem.

Abstract: Whether or not protection circuitry for a span-powered remote digital subscriber loop unit is properly connected to earth ground is determined by the deliberate assertion and detection of a ground fault from a central office line card location. The span-powered remote unit is augmented to place a controllable conduction path in circuit with the span-powered loop and an earth ground pin. If the earth ground pin has been properly connected to earth ground, applying the conductive path will place a ground fault on the span, which is detected by a ground fault detector within the central office line card. If the ground fault detector does not detect a ground fault in response to the application of the conductive path, the line card forwards a negative ground fault event message to a test center, so that a service technician may be dispatched to the remote unit to correct the problem.

Abstract: An echo canceler for a fractionally spaced telecommunication receiver employs a signal estimator, which generates a fractionally spaced representation of a received information signal that has been subjected to Tomlinson preceding. The output of the signal estimator is differentially combined with fractionally spaced outputs of the echo canceller, so as to effectively remove the contribution of the received information signal from the echo cancellation update operation. As a result, the echo update signal will consist primarily of the residual echo and the noise from the wireline/loop. The error signal can be used at the fractional spacing rate to update all of the echo canceler coefficients, largely without interference from the much larger received information signal. This allows a higher echo canceler gain than that currently incorporated into HDSL2 echo canceler updates.

Abstract: A binary decision tree-based arbitration scheme executable by a control processor of a time division multiplex (TDM)-based communication system is operative to select the next packet to be transmitted from a plurality of virtual circuits, any number of which may have one or more packets awaiting transmission over a serialized digital communication link. The transmission priority scheme contains N+1 sets of nodes containing 2N+1?1 nodes. A respective ith set of nodes comprises 2i?1 nodes, wherein i is greater than or equal to 1, and less than or equal to N+1. The nodes of a given set are connected to those of an adjacent set by binary-split branches. For each of the 2N leaf nodes of the decision tree, information is stored representative of the transmission priority of a packet awaiting transmission from its associated communication port.

Abstract: A redundant communication system contains a principal transceiver and a back-up transceiver to be controllably substituted for the principal transceiver. A monitor protection switch, which controls swapping the two transceivers, has an RF loopback test circuit that is switchably coupled to whichever transceiver is the back-up. The RF loopback test circuit monitors the operational capability of the back-up transceiver, and provides an indication of its functionality. If the back-up transceiver is defective, corrective action can be taken in advance of a potential operational failure of the principal transceiver. As long as the RF loopback test circuit indicates proper operational capability of the back-up transceiver, the redundant transceiver can be immediately switched in place of the principal transceiver.

Abstract: A method and apparatus for adaptively adjusting the parameters of a timing loop based upon frequency errors between a data signal and a receiver's clock that is being used to sample the data signal are provided by the present invention. In accordance with the invention, the timing loop parameters are first set to an initial set of parameter values. A current frequency error between the data signal and the receiver's clock is calculated. The approximate average value of the frequency error is then determined. After a predetermined amount of time, the absolute value of the difference between the average frequency error and the current frequency error is examined. If the absolute value of the difference is less than a specified threshold, the timing loop parameters are reset to a second set of parameter values contained in a memory. The timing loop parameters are then reset to a third set of parameter values after a second interval of time.

Abstract: Adaptive clock recovery for the receiving entity of a communication system transporting constant bit-rate (CBR) services over an asynchronous transfer mode (ATM) or ATM-like network is performed by a digital phase locked loop (DPLL). The recovered clock is based on the DPLL's phase detector's count of high frequency service clock cycles between transitions in an input signal representative of instances of receipt of ATM cells subject to cell delay variations through the network, and a reference clock signal whose frequency is a prescribed fraction of that of the output clock. The DPLL's VCO function is an increment/decrement of the service clock frequency, which avoids constraining the operation of a high performance modem (such as a V.90 modem).

Abstract: A multi-circuit emulating line card is installable in a single line card slot of the backplane of digital switch, and is configured to emulate the functionality of each of a plurality of digital switch line cards, respectively associated with plural digital subscriber circuits served by the switch. In the course of emulating these plural line cards, the multi-circuit line card provides connectivity between each digital subscriber circuit and a digital carrier communication link to plural digital subscriber loop circuits, such as BRITE cards of a remote terminal site. The line card of the invention also includes network and subscriber circuit-associated metallic link impedance simulation circuits for terminating a metallic test bus.

Abstract: A central office transceiver-installed current limiter and regulator provides fault isolation and transient load isolation in a wireline communication network, having multiple transceivers connected by respective span-powered wirelines to a common power source at the central office. Using a current-sense resistor and controlled switch in series with the wireline, the current-limiter and regulator processes input electrical power from the power source prior to coupling that power to a remote transceiver. To prevent overheating and substantial power dissipation in the current-limiting circuitry in the event of a prolonged fault condition, the controlled switch is alternately turned on and off.

Abstract: A timing loop is used in a data communications receiver to time lock the receiver to a transmitter sending data across a communications loop, where the receiver includes a linear equalizer for correcting signal distortion associated with the communications loop. The timing loop includes a timing equalizer filter functionally positioned to provide an equalized signal to the phase detector portion of the timing loop. After the linear equalizer trains, the equalizer coefficients are copied to the timing equalizer.

Abstract: To locate an open fault along a telecommunication wireline pair, a prescribed frequency tone is coupled to the wireline pair by way of a center tap of the transformer through which a line card is coupled to a subscriber loop. The line card's analog front end conducts capacitance to ground measurements on the tip and ring segments of the wireline pair. From these measurements, sum and difference distance values of respective tip and ring conductor lengths are derived. The sum and difference distance values are then processed to calculate the distance to the fault.

Abstract: An arrangement for interfacing signals between a control processor of a digital communication equipment shelf and diverse types of telecommunication equipment includes a multipin communication port that is configured to be coupled by way of a communication cable to either data communication equipment or data terminal equipment. A relay switch is coupled to the multipin communication port and is operative, under processor control, to selectively terminate internal leads of the multipin communication port to first and second sets of communication source/terminations, respectively associated with data communication equipment and data terminal equipment.

Abstract: An RF loopback test circuit is adapted to be coupled to an antenna port of a digital radio, to determine whether the radio is functioning properly. A frequency generator outputs an auxiliary frequency corresponding to the sum or difference between the radio's transmit and receive frequencies. The auxiliary frequency is coupled to a Schottky diode mixer, which is also coupled to the input/output port. If the radio's transceiver section is operating properly, the sum or difference frequency output of the Schottky diode mixer will be passed by only the diplexer's narrowband receive path filter to the radio's receiver section. The mixer's sum frequency is blocked by the diplexer's narrowband filters. Therefore, if the receiver section provides an indication that it is receiving a sufficient signal level from the RF loopback test circuit, it can also be inferred that each of the transmitter and receiver sections is operating properly.

Abstract: A communication system for transmitting (T1) digital communication signals between a transmit site and a receiver site includes an M:1 multiplexer, coupled to a rate 1/N convolutional encoder, which is operative to output an encoded output signal modulated in quaternary phase shift keyed (QPSK) space having a prescribed symbol rate. The receive site has a rate 1/N Viterbi decoder which is operative to decode the encoded output signal output by the rate 1/N convolutional encoder, and a 1:M demultiplexer having an input coupled to the Viterbi decoder and M plurality of outputs, and being operative to demultiplex the decoded signal from the Viterbi decoder into a plurality of M time division multiplexed digital communication signals. For any selected values for of M and N, the product of M and N is constant.

Abstract: A measure is derived of the potential alignment of radio antennas associated with wireless transceivers, that are interfaced with terrestrial communication links transporting digital communication signals between geographically spaced apart transceiver sites. At a first radio site, a received signal strength indication is derived for signals sourced from a second radio site geographically remote with respect to the first site. In addition, received signal quality is measured on signals sourced from the second site. A measure of how well a first radio antenna at the first site is aimed in the direction of a second radio at the second site is derived in accordance with the received signal strength indication and the received signal quality measurement.

Abstract: A current-regulating driver circuit for a light emitting diode (LED) maintains energization drive to and thereby illumination provided by the LED at a prescribed, substantially constant value, over a relatively wide range of input (AC or DC) voltage. First and second input nodes are coupled to a source of AC or DC voltage and to a load, powered by the source of AC or DC voltage. An input rectifying diode is coupled to the first input node. A controlled current flow element is coupled in a first current flow path between the input rectifying diode and the LED and is controllably operative to supply current for illuminating the LED.