Abstract: In addition using twenty-four DS0 channels of an E1 transport rate-based digital communication link to convey an entire T1 frame of voice/data channels, an additional 364 Kbps bandwidth is used to convey a plurality of (up to six) DS0 data channels, without having to modify the signaling properties of the T1 frame into the higher transport rate protocol. For non-primary T1 voice channels, robbed encoded signaling bits are inserted ‘as is’ into the E1 signaling channel and mu-law encoded voice is inserted into 24 DS0 channels of the E1 frame. For primary rate ISDN (having no robbed bits), the signaling channel of the E1 frame becomes available for any ISDN channel. This allows the ‘D’ channel of the ISDN frame to be inserted in any of the thirty-one available E1 time slots.

Abstract: A central office transceiver-installed current limiter and regulator provides fault isolation and transient load isolation in a wireline communication network, having multiple transceivers connected by respective span-powered wirelines to a common power source at the central office. Using a current-sense resistor and controlled switch in series with the wireline, the current-limiter and regulator processes input electrical power from the power source prior to coupling that power to a remote transceiver. To prevent overheating and substantial power dissipation in the current-limiting circuitry in the event of a prolonged fault condition, the controlled switch is alternately turned on and off.

Abstract: A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output.

Abstract: A comparator-based switchmode power converter monitors the most negative of the tip and ring line voltages, to control the supply voltage to a SLIC. The voltage applied to the SLIC's power terminals is slightly higher than the sensed voltage for different loop signaling conditions, including loop start, ground start balanced ringing. The switchmode converter includes a comparator coupled to a DC-DC output node downstream of a MOSFET switch installed in a DC supply rail of a source of DC supply voltage, and coupled to a power supply terminal of the SLIC. The comparator is also coupled to a set point node, which is coupled through a voltage offset path to each of tip and ring portions of the telephone line.

Abstract: To reduce the possibility of a data-induced latching loopback, a digital data services device integrates one or more digital control code-based filtering routines into a test code sequence-based latching loopback scheme. The filtering routines include a ‘garbage’ byte detection routine, a ‘protected loopback’ routine, and a ‘preamble’ routine. The ‘garbage’ byte detection routine is an intra-loopback establishment filtering routine that limits the type of customer data that may be received between sequences of repeated control bytes of a valid latching loopback sequence. The ‘protected loopback’ routine is a flag byte-based filtering routine for frame relay data, which controllably disables latching loopback for a prescribed period of time, whenever a predetermined character associated with frame relay customer data is detected.

Abstract: The present invention of a power supply and battery back-up system includes an AC/DC power supply and a battery for supplying operating power to a telecommunications system. The battery is connected to the telecommunications system and is designed to supply the telecommunications system with operating power if the power supply fails for some reason. The power supply is designed to output the peak operating power required by the telecommunications system, supplying the telecommunications system with whatever operating power it needs and supplying the difference between the operating power supplied to the telecommunications system and the peak operating power output by the power supply to the battery for charging. In one embodiment, the battery back-up system includes a battery monitoring circuit for monitoring the battery voltage and a relay connected between the battery and the telecommunications system for disconnecting the battery if the battery voltage falls below a pre-set level.

Abstract: A ringing voltage power management circuit is configured to extract an isolated high-value intermediate voltage from a central office powered digital subscriber line through a current limiting circuit, and to charge a storage capacitor that serves as an energy reservoir for the ring generator of a subscriber line circuit. The storage capacitor and the current limiting circuit isolate the peak power drawn by the ringing load from the telephone line and translate the ringing signal's (20 Hz) ripple to the sub-Hz oscillations of the ringing cadence.

Abstract: An automated data rate detection mechanism examines bit contents of a data frame to identify the number of idle bytes (0111 1110). When no data is transmitted, an all ‘1’s bit pattern (1111 1111) occupies other time slots unused by the customer's device. The number of subscribed DS0 (64 kbps) increments is determined by looking for the first idle byte following all ‘1’s bytes, and counting the number of zero bits until further unused (all ‘1’s) DS0s are encountered. Dividing the total number of zeros counted by two represents the number ‘n’ of assigned DS0 increments. Multiplying this number ‘n’ by the bit rate per DS0 channel (64 kbps) yields the bit rate.

Abstract: A non-linear echo cancellation scheme for a digital transceiver coupled to a wireline medium effectively mitigates against non-linear line perturbations that may cause disruption of digital communication services. A first embodiment employs a fast, linear echo canceler, and a truncated non-linear Volterra canceler coupled to an error cancellation location in the data signal flow path downstream of the data pump's linear equalizer. A second embodiment employs only a nonlinear Volterra echo canceler, the output of which is coupled to an error cancellation location in the data signal flow path upstream of the data pump's linear equalizer. A third embodiment employs a linear echo canceler with high gain setting on selected taps, and a truncated non-linear Volterra canceler coupled to an error cancellation location in the data signal flow path downstream of the data pump's linear equalizer.

Abstract: In order to configure and monitor the operation of a span-powered T1 radio, use is made of the out-of-band facility data link channel that is available within an extended superframe of the T1 digital data stream transported between an indoor carrier services unit and the T1 framer of the radio. The facility data link channel is employed to transport packetized configuration and status information between the indoor carrier service unit and the span-powered T1 radio.

Abstract: A method and apparatus for providing a precoder filter having peak-to-average ratio (PAR) controller that also serves as a high-pass, low-pass, or band-pass filter. The described invention is includes a modulo device connected in series with the PAR controller and a precoder filter connected in a feedback arrangement. The input to the apparatus is a sequence of data symbols and the output is a spectrally shaped precoded signal having a controlled peak-to-average ratio.

Abstract: A system for provisioning a network access device based on control settings received from a remote location utilizes logic and memory for storing a set of operational control settings and a set of default control settings for the network access device. The logic is configured to store, in the memory, the operational control settings based on data received from a remote device via a network. The logic is configured to control the network access device based on the operational control settings and to begin controlling the network access device based on the default control settings in lieu of the operational control settings in response to a determination that the network access device is unable to communicate over the network based on the operational control settings, thereby enabling the network access device to be remotely re-provisioned.

Abstract: A communication control mechanism installable in the communications controller of an ISDN terminal adapter is operative to conduct in-band communications with its digital terminal device during an internet communication session between the digital terminal device and a digital communication network interface of an internet service provider. The terminal adapter monitors the data link establishment communication exchange between the network access server and the personal computer, to identify and capture internet protocol addresses for the digital terminal device and the network access interface. These addresses are then used by the terminal adapter to communicate in-band with the digital terminal device using user datagram protocol (UDP)-based messages.

Abstract: A bidirectional serial TDM backplane—UTOPIA interface contains an ATM cell boundary location and transmit flow control mechanism, to provide for the efficient capture and storage of ATM cells from a serial TDM channel. Once stored in a transmit buffer, individual ATM cells are controllably read out for application to a downstream UTOPIA interface. In the upstream direction from the UTOPIA bus toward the serial TDM backplane, ATM cells are stored in a multi-cell receive buffer, so that they may be serialized for application to the TDM backplane. In the absence of ATM data cells to transfer, unfilled timeslots are filled with idle cells to maintain the ATM bus active.

Abstract: A mechanism for implementing a single-interrupt-based voice playout buffer transfer operation. The contents of each respective channel of a multi-channel voice playout buffer are encapsulated so as to prepend a four byte ATM header, a HEC byte, and a four byte AAL2 header to a forty-four byte voice channel field to realize a standard fifty-three byte ATM cell. Within the AAL2 header, a channel identification byte (CID) provides selective mapping to timeslots of a TDM frame, to accommodate variations among different vendor equipments. The next to last bit of the last byte of the ATM header is used as an interrupt to the network processor. Only the highest voice channel asserts this next to last bit as an interrupt bit.

Abstract: A voice playout buffer for a dual PHY-based integrated access device platform has a plurality of voice signal buffer sections. A respective buffer section has a capacity in excess of the number of digitized voice signal bytes contained in a respective cell-based communication signal. A respective buffer section sequentially stores digitized voice signals of a single TDM channel into successive storage locations of a first portion thereof at a first data rate, and reads out digitized voice signals at a second, higher data rate for transport over an ATM cell bus. The storage capacity of a buffer section accommodates a communications control processor writing new outgoing digitized voice signal bytes into the first portion of the voice signal buffer section for transport over a TDM communication link, prior to digitized voice signals newly received from the TDM communication link being written into the first portion of the voice signal buffer section.

Abstract: At a transmit site of an inverse multiplexing system, an input demultiplexer demultiplexes high bandwidth serial communication signals (e.g., fractional T3 rate signals) into communication signal packets for transmission over reduced bandwidth serial communication (e.g. T1) channels. A multiplexer for each channel combines successive packets of demultiplexed signals with bits of multibit packet reassembly control words that identify the channel and the order in which communication signal packets have been demultiplexed, to produce successive frames for transmission over the channel. At a receiver site the control words are extracted from the frames of data and analyzed to control reassembly of the serial data packets into their original order.

Abstract: A dual PHY-based integrated access device (IAD) platform employs a highly integrated time division multiplexed (TDM), a synchronous transfer mode (ATM) cell based architecture, to provide enhanced interfacing flexibility for multiple and diverse signaling protocols, effectively reducing the cost and constraints as to choice of host processor used in conventional digital signal processor (DSP)-based IADs. With the signaling transport speed of the dual PHY based path being an order of magnitude greater than that of any of the plurality of communication paths with which the IAD is interfaced, the IAD of the invention provides effectively real time support for different communication requirements, including TDM, ATM, HDLC, and the like.

Abstract: A comparator-based switchmode power converter monitors the most negative of the tip and ring line voltages, to control the supply voltage to a SLIC. The voltage applied to the SLIC's power terminals is slightly higher than the sensed voltage for different loop signaling conditions, including loop start, ground start balanced ringing. The switchmode converter includes a comparator coupled to a DC-DC output node downstream of a MOSFET switch installed in a DC supply rail of a source of DC supply voltage, and coupled to a power supply terminal of the SLIC. The comparator is also coupled to a set point node, which is coupled through a voltage offset path to each of tip and ring portions of the telephone line.

Abstract: A back-up channel line card-installed ESF framing mechanism independently sources an FDL signaling channel for the transport of protection switch signaling information, taking advantage of the fact that DSL multiplexer equipment is capable of accepting and processing ESF framed digital data, including embedded FDL-based signaling information. Upon completion of transport of the FDL-based signaling information, the back-up channel is used for data transport in place of a faulty channel.