Abstract: A clock recovery scheme for a digital communication receiver has a fixed fractional delay line that is driven by a fixed frequency reference clock source, to provide a plurality of respectively offset phase delayed versions of the reference clock. A phase lock loop, to which the received signal is coupled, controllably steps through the phase delayed versions of the reference clock, so as to controllably increase or decrease the effective frequency of the reference clock and thereby produce a recovered clock signal.
Type:
Application
Filed:
July 15, 2003
Publication date:
January 20, 2005
Applicant:
ADTRAN, INC.
Inventors:
Matthew Kliesner, Timothy Mester, Eric Rives
Abstract: A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide respectively different phase delayed versions of the input clock signal and feeds a multiplexer that is controllably operative to couple one of the outputs of the fixed fractional delay line to a regenerated clock output port. A control loop, which includes the FIFO storage buffer, the output port and a steering control input of the multiplexer circuit, is operative to selectively change which output of the fixed fractional delay line is coupled by the multiplexer to the output port, so as to controllably cause the output clock signal to track the effective frequency of the valid data signal.
Type:
Application
Filed:
July 15, 2003
Publication date:
January 20, 2005
Applicant:
ADTRAN, INC.
Inventors:
Matthew Kliesner, Timothy Mester, Eric Rives
Abstract: A query message-based call routing mechanism for a limited access cooperative telecommunication network initially determines whether the called party is commonly located at the same node as the calling party. If not, the calling party node broadcasts a query message to all other nodes in the network to locate the called party. Only the node having local knowledge of the called extension will reply to the query message. Once the node sourcing the query message has received this reply message, it will place a call to the node servicing the called extension.
Abstract: A system for protecting configuration data of a programmable execution unit (PEU) comprises a programmable array and programming logic. The programming logic is configured to receive configuration data and to program the programmable array, based on the configuration data, such that the programmable array comprises functional logic and activation logic. The activation logic is configured to enable the functional logic upon detection of an activation key.
Abstract: A redundant ringing signal generator subdivides a ringing signal bus into multiple ringing bus segments. A plurality of redundant ringing voltage generators sourcing internally and/or externally ringing voltages are individually and selectively connectable to the multiple ringing bus segments. In the event of a prescribed anomaly in the ringing signal sourced by a ringing generator, the faulty ringing signal is automatically disconnected from its associated ringing bus segment, and that ringing bus segment is connected to a redundant ringing signal source, provided by either the same or another ringing generator.
Type:
Grant
Filed:
April 12, 2000
Date of Patent:
November 2, 2004
Assignee:
Adtran, Inc.
Inventors:
Steven M. Robinson, John S. McGary, Ralph R. Boudreaux, Jr.
Abstract: An operational condition capture mechanism within the communications control processor of an integrated access device stores in non-volatile (flash) memory prescribed state information associated with the operation of the communications control processor, in response to a catastrophic event that initiates a reboot of the device, and thereby interruption of the transmission of digital communication signals by the integrated access device, so as to facilitate subsequent off-line analysis (e.g., trouble-shooting) of the cause of the misoperation of the device, and interruption of digital communication service.
Type:
Application
Filed:
April 14, 2003
Publication date:
October 28, 2004
Applicant:
ADTRAN, INC.
Inventors:
Christopher A. Otto, Phillip Stone Herron, Ian D. Locy
Abstract: A digital data demodulator employs a cordic rotator-based, digital phase locked loop for carrier frequency tracking. Digitized I and Q channels downconverted to baseband using a fixed frequency oscillator are coupled to a digital cordic rotator. The cordic rotator iteratively executes pipelined phase-rotational adjustments of its digitized in-phase and quadrature inputs, in association with a pipelined reduction of the accumulated value of a phase angle vector code generated by digital phase error detection logic circuitry to which rotated I and Q outputs of the cordic rotator are applied. The phase error representative code vector is coupled through a digital loop filter as a reference angle input to the cordic rotator. The cordic rotator iteratively rotates the I and Q channel values that reduce the accumulated phase error to zero.
Type:
Application
Filed:
May 5, 2004
Publication date:
October 21, 2004
Applicant:
Adtran, Inc.
Inventors:
Eric M. Rives, Matthew F. Gann, Anthony A. Goodloe
Abstract: The potential threat to digital radio baseband equipment from excessive currents in an electrical communication cable, due to a lightning strike at or near the top of an RF transceiver tower is avoided by replacing the electrical cable with a non-electrical signaling path, in particular a fiber optic signaling path. Power for the RF transceiver is conveyed to the tower in a separate electrical link. This serves to effectively electrically isolate baseband equipment from a potential source of potential lightning strikes, while at the same time providing full intra-communication connectivity within the digital radio.
Abstract: Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.
Abstract: A high bit rate digital subscriber line (HDSL) communications scheme employs a serialized multiplexer—demultiplexer protocol, that enables both HDSL channels to be successfully transmitted over an asynchronous, serialized communication link. A service channel supplies control information used by a far end device to extract each HDSL channel from the serialized bit stream. A data channel interface circuit combines a pair of data channel segments of two 784 kbps HDSL channels into a standard 1.544 Mbps T1 serial data stream. The data channel interface circuit contains a register bank which stores embedded operations channel (EOC) information extracted from the two HDSL channels. Auxiliary HDSL signaling information stored in the data channel interface circuit is controllably accessed by a communications control processor for application to an output multiplexer.
Abstract: A power supply system has redundant regulated power supplies, whose output ports are diode-ORed to an output node. One of the power supplies outputs a regulated output voltage that is sufficient to meet current demand of a load coupled to the output node. Each power supply has an associated monitoring circuit that monitors the voltage drop across its OR-ing diode. The monitoring circuit for a non-dominant power supply controls its operation so that the non-dominant supply provides a reduced current through its diode to the output node that is less than the current demand of the load, but sufficient to forward bias the diode, and thereby enable the non-dominant supply to immediately respond to a load change, such as an interruption in the operation of the dominant power supply.
Type:
Grant
Filed:
January 16, 2002
Date of Patent:
October 5, 2004
Assignee:
Adtran, Inc.
Inventors:
Erik Stefan Bahl, John S. McGary, Jason P. Lyon
Abstract: Whether or not protection circuitry for a span-powered remote digital subscriber loop unit is properly connected to earth ground is determined by the deliberate assertion and detection of a ground fault from a central office line card location. The span-powered remote unit is augmented to place a controllable conduction path in circuit with the span-powered loop and an earth ground pin. If the earth ground pin has been properly connected to earth ground, applying the conductive path will place a ground fault on the span, which is detected by a ground fault detector within the central office line card. If the ground fault detector does not detect a ground fault in response to the application of the conductive path, the line card forwards a negative ground fault event message to a test center, so that a service technician may be dispatched to the remote unit to correct the problem.
Type:
Application
Filed:
March 31, 2003
Publication date:
September 30, 2004
Applicant:
ADTRAN, INC.
Inventors:
Bradley Dwayne Tidwell, Steven M. Robinson, James Michael Hawkins
Abstract: A test fixture interfaces plural units under test (UUTs) with test equipment within a common equipment rack. The test fixture supports a plurality of vertically spaced apart shelf units. A shelf unit has a support surface and an input/output connector panel adjacent thereto, that define a UUT insertion cavity. An input/output connector panel contains cable terminations that terminate cables to various testing equipments. Insertion of a UUT into the insertion cavity places communication ports of the UUT adjacent to cable terminations of the adjacent input/output connector panel. Jumper cables interconnect communication ports of the UUT with cable terminations of the adjacent input/output connector panel.
Type:
Application
Filed:
February 19, 2003
Publication date:
August 19, 2004
Applicant:
ADTRAN, INC.
Inventors:
Phillip H. Ewing, Marc L. Roth, Paul L. Wooten
Abstract: An upstream transceiver, coupled to an upstream end of a long haul, single digital subscriber loop of an extended range asymmetrical digital subscriber line communication system, ‘spoofs’ a (co-located) digital subscriber line access multiplexer to reduce its downstream data rate over a short haul loop to the upstream transceiver. The reduced downstream data rate is compatible with the data rate that can be supported by the long haul loop and also accommodates an auxiliary (64K) POTS channel thereover. The reduced data rate may be derived by preliminary signal quality measurements upon the long communication loop conducted between the upstream transceiver and a downstream transceiver coupled to a remote end of the long haul loop.
Type:
Grant
Filed:
July 20, 2001
Date of Patent:
August 10, 2004
Assignee:
Adtran, Inc.
Inventors:
Thomas L. Ballard, III, John B. Wilkes, Jr., Kevin W. Schneider
Abstract: A digital data demodulator employs a cordic rotator-based, digital phase locked loop for carrier frequency tracking. Digitized I and Q channels downconverted to baseband using a fixed frequency oscillator are coupled to a digital cordic rotator. The cordic rotator iteratively executes pipelined phase-rotational adjustments of its digitized in-phase and quadrature inputs, in association with a pipelined reduction of the accumulated value of a phase angle vector code generated by digital phase error detection logic circuitry to which rotated I and Q outputs of the cordic rotator are applied. The phase error representative code vector is coupled through a digital loop filter as a reference angle input to the cordic rotator. The cordic rotator iteratively rotates the I and Q channel values that reduce the accumulated phase error to zero.
Type:
Grant
Filed:
March 30, 2000
Date of Patent:
August 3, 2004
Assignee:
Adtran, Inc.
Inventors:
Eric M. Rives, Matthew F. Gann, Anthony A. Goodloe
Abstract: A programmable network-DTE interface integrates T1/E1 framer, data pump and microprocessor components into a common subsystem chip architecture, and interfaces each of these components by means of a user programmable multiplexing subsystem, so as to allow any of the functional blocks of the architecture to be selectively enabled or disabled/by-passed by the user.
Type:
Application
Filed:
January 8, 2003
Publication date:
July 8, 2004
Applicant:
ADTRAN, INC.
Inventors:
Charles David Capps, Clarke Edgar Moore, Dwight Edwin Wright
Abstract: A shared T1/E1 signaling bit processor interfaces with either T1 or E1 traffic, and controllably performs robbed bit signal extraction and insertion for T1/E1 signaling protocol using a common set of input/output circuitry and associated decode/control logic therefor. A receiver subsystem controllably samples and extracts signaling bits from selected time slots within serial frames of data incoming from the network to the DTE for delivery to the control processor; a transmitter subsystem controllably inserts signaling bits into selected signaling channels of serial frames of data outgoing from the DTE to the network.
Type:
Application
Filed:
January 8, 2003
Publication date:
July 8, 2004
Applicant:
ADTRAN, INC.
Inventors:
Clarke Edgar Moore, Dwight Edwin Wright
Abstract: The present invention provides an apparatus and method for universal decoding of both feedforward codes and feedback codes, such as decoding of a 512-state feedforward code, a 32-state feedback code and 8-state feedback code. Utilizing parallel processing, the present invention determines, for each current state of a feedforward or a feedback code, its most likely previous states, resulting in a determination of a terminating state and a penultimate terminating state. From the penultimate terminating state and terminating state, associated subset bits are determined. In the preferred embodiment, the subset bits are determined by re-encoding the most significant bit of the penultimate terminating state in an encoder having a current state equal to the terminating state. Utilizing an equalized, received signal, a closest signaling point, with an associated index, is selected from a subset of a signaling constellation corresponding to the associated subset bits.
Abstract: A cable balance network for use in a full-duplex telecommunication system and method for optimizing the transhybrid loss of a full-duplex to half-duplex conversion circuit, said cable balance network comprising: (a) a plurality n of resistors Rn, each of said resistors Rn having a fixed resistance value dependent upon the impedance seen by the full-duplex port, and each of said resistors Rn, having a positive node and a negative node; (b) a plurality n−1 of capacitors Cn−1, each of said capacitors Cn−1 having a fixed capacitance value dependent upon the impedance seen by said full-duplex port, and each of said capacitors Cn−1 having a positive node and a negative node; and (c) a circuit configuration comprising at least two of said resistors R1, and R2 (n≧2) and at least one of said capacitors C1, such that all the negative nodes of each of said resistors Rn are effectively connected together, and such that the capacitor Cn−1is connected between the positive nodes of resistors
Abstract: A ‘lifeline’ POTS back-up mechanism is operative to provide emergency plain old telephone service connectivity over a span-powered two-wire metallic digital subscriber loop pair, in response to a customer's phone going off-hook, during a lack of normal operating condition of the digital circuit path. A ground fault interruption signal is generated in a remote terminal and used to activate respective POTS by-pass paths in the remote terminal and a central office terminal.
Type:
Grant
Filed:
January 7, 2000
Date of Patent:
June 29, 2004
Assignee:
Adtran, Inc.
Inventors:
John B. Wilkes, Jr., Steven M. Robinson