Patents Assigned to Advanced Micro Devices, Inc.
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Patent number: 12249519Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.Type: GrantFiled: June 17, 2022Date of Patent: March 11, 2025Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Priyal Shah, Milind S. Bhagavat, Brett P. Wilkerson, Lei Fu, Rahul Agarwal
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Patent number: 12250493Abstract: Machine learning-based multi-view video conferencing from single view video data, including: identifying, in video data, a plurality of objects; and generating a user interface comprising a plurality of first user interface elements each comprising a portion of the video data corresponding to one or more of the plurality of objects.Type: GrantFiled: May 25, 2023Date of Patent: March 11, 2025Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Roto Le
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Patent number: 12248516Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.Type: GrantFiled: February 8, 2024Date of Patent: March 11, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Ganesh Dasika, Michael Ignatowski, Michael J Schulte, Gabriel H Loh, Valentina Salapura, Angela Beth Dalton
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Patent number: 12248423Abstract: An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by replacing the original transaction identifier associated with the incoming transaction request and sends the retagged incoming transaction request to a target. A returned response is received from the target. The retag transaction ID in the returned response is removed and replaced with the original transaction ID before being sent as a reply to the requesting unit. Associated methods are also presented.Type: GrantFiled: February 2, 2023Date of Patent: March 11, 2025Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Buheng Xu, Dong Yu, Philip Ng, Lianji Cheng
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Patent number: 12248789Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.Type: GrantFiled: April 28, 2023Date of Patent: March 11, 2025Assignee: Advanced Micro Devices, Inc.Inventor: Maxim V. Kazakov
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Patent number: 12250379Abstract: A method and an apparatus for decoding an image are disclosed. A region of the image is selected and the decoding is selected region and associated metadata is performed. Pixels for a generated for a decoded image based on the decoded selected region and metadata.Type: GrantFiled: November 11, 2022Date of Patent: March 11, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Andrew S. Pomianowski, Konstantine Iourcha
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Publication number: 20250077379Abstract: Techniques for performing memory operations are disclosed herein. The techniques include obtaining statistics for operation of a device, the statistics including either or both of performance statistics and memory access statistics; generating a plurality of visualizations of the statistics in one of an overlay mode or a scene annotation mode; and displaying the plurality of visualizations.Type: ApplicationFiled: September 4, 2023Publication date: March 6, 2025Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Guennadi Riguer, Christopher J. Brennan
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Publication number: 20250077320Abstract: A message passing interface processing system is described. In accordance with message passing logic, a node selects an affinity domain for communication of data associated with a message passing interface and selects a first rank of a first process of the message passing interface assigned to a first partition of the affinity domain as a first partition leader rank and an affinity domain leader rank. The node selects a second rank of a second process of the message passing interface assigned to a second partition of the affinity domain as second partition leader rank, receives the data at the first partition leader rank, and communicates the data from the first partition leader rank to the second partition leader rank.Type: ApplicationFiled: August 30, 2023Publication date: March 6, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Nithya Viswanathan Shyla, Manu Shantharam
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Publication number: 20250077307Abstract: In accordance with the described techniques, a command processor processes a fiber graph that includes fibers each having one or more tasks and indicates dependencies between the fibers and between tasks within the fibers. As part of this, the command processor dispatches a task from a fiber for execution by a processing element array based on the fiber being enqueued in a ready queue and the dependencies of the task being resolved. While the task is dispatched and unexecuted by the processing element array, the command processor enqueues the fiber in a sleep queue. Further, the command processor enqueues the fiber in a check queue based on the one or more tasks of the fiber having been executed by the processing element array. Based on the fiber being in the check queue, the command processor enqueues a dependent fiber in the ready queue that depends from the fiber.Type: ApplicationFiled: August 31, 2023Publication date: March 6, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Ali Arda Eker, Martha Massee Barker, Anthony Thomas Gutierrez
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Patent number: 12242828Abstract: A compilation technique is provided. The technique includes including a first instruction into a first executable for a first auxiliary processor, wherein the first instruction specifies execution by the first auxiliary processor; and including a second instruction into the first executable, wherein the second instruction targets resources that have affinity with the first auxiliary processor.Type: GrantFiled: November 1, 2022Date of Patent: March 4, 2025Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Mingliang Lin
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Patent number: 12242893Abstract: A system and method for ranking computing resources in a distributed computing marketplace is disclosed. Ranking may be based on the performance factors that the system predicts will have the greatest impact on the particular application the user plans to run. A performance database stores historical performance data for applications that have been executed on multiple different computer systems. The database is checked to see if the application, or one similar, has already been run on any of the computing systems participating in the distributed computing marketplace. If so, the existing performance data is used to predict which performance factors will have the greatest impact on the application. Those factors are then used to rank the available computing systems options for the user.Type: GrantFiled: August 18, 2021Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Max Alt, Gabriel Martin
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Patent number: 12242407Abstract: An exemplary data fabric device comprises a first traffic moderator configured to receive traffic destined for a specific endpoint accessible via a plurality of data paths and divert the traffic from a first data path included in the data paths to a second data path included in the data paths. The exemplary data fabric device also comprises a first interconnect controller that resides within the second data path and is configured to forward the traffic to the specific endpoint via a first communication link to test a functionality of the first communication link. Various other apparatuses, systems, and methods are also disclosed.Type: GrantFiled: November 8, 2022Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Samuel Abraham Lipson, Eric Christopher Morton, Bryan P. Broussard, Vydhyanathan Kalyanasundharam
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Patent number: 12242384Abstract: Methods, devices, and systems for prefetching data. First data is loaded from a first memory location. The first data in cached in a cache memory. Other data is prefetched to the cache memory based on a compression of the first data and a compression of the other data. In some implementations, the compression of the first data and the compression of the other data are determined based on metadata associated with the first data and metadata associated with the other data. In some implementations, the other data is prefetched to the cache memory based on a total of a compressed size of the first data and a compressed size of the other data being less than a threshold size. In some implementations, the other data is not prefetched to the cache memory based on the other data being uncompressed.Type: GrantFiled: January 27, 2023Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Pazhani Pillai, Harish Kumar Kovalam Rajendran
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Patent number: 12243576Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.Type: GrantFiled: May 17, 2023Date of Patent: March 4, 2025Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Jing Wang, Kedarnath Balakrishnan, Kevin M. Brandl, James R. Magro
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Patent number: 12243578Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.Type: GrantFiled: December 20, 2023Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Karthik Gopalakrishnan, Tsun Ho Liu
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Patent number: 12242325Abstract: Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.Type: GrantFiled: March 30, 2022Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: William Robert Alverson, Amitabh Mehra, Jerry Anton Ahrens, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
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Patent number: 12235756Abstract: Near-memory compute elements perform memory operations and temporarily store at least a portion of address information for the memory operations in local storage. A broadcast memory command is then issued to the near-memory compute elements that causes the near-memory compute elements to perform a subsequent memory operation using their respective address information stored in the local storage. This allows a single broadcast memory command to be used to perform memory operations across multiple memory elements, such as DRAM banks, using bank-specific address information. In one implementation, the approach is used to process workloads with irregular updates to memory while consuming less command bus bandwidth than conventional approaches. Implementations include using conditional flags to selectively designate address information in local storage that is to be processed with the broadcast memory command.Type: GrantFiled: December 21, 2021Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Shaizeen Aga, Johnathan Alsop, Nuwan Jayasena
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Patent number: 12236134Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.Type: GrantFiled: September 27, 2022Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Mahzabeen Islam, Shaizeen Dilawarhusen Aga, Johnathan Robert Alsop, Mohamed Assem Abd ElMohsen Ibrahim, Nuwan S Jayasena
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Patent number: 12237286Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.Type: GrantFiled: August 25, 2023Date of Patent: February 25, 2025Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Rahul Agarwal
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Patent number: 12238872Abstract: Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a circuit board is provided that has a substrate with a pocket and a conductor layer. A chiplet is positioned in the pocket. The chiplet has plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips.Type: GrantFiled: February 8, 2022Date of Patent: February 25, 2025Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Robert N. McLellan
