Patents Assigned to Advanced Micro Devices, Inc.
  • Patent number: 6569694
    Abstract: A novel method is provided for checking BGA substrate design made using an APD design tool. User's netlist containing information on a die to be mounted on the BGA substrate is entered into an interface software system providing an interface to the APD design tool. The interface software system extracts the design netlist generated from the APD design of the BGA substrate, and compares this netlist to the user's netlist. If no differences are reported, the BGA substrate design is considered to be correct.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: May 27, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pranabendra Sarma, Alexander Tain, Valerie Vivares
  • Patent number: 6569747
    Abstract: Shallow trench isolation techniques are disclosed in which a nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate. The nitride layer is removed prior to filling the isolation trench, and the fill material is planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: May 27, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Kashmir Sahota
  • Patent number: 6570787
    Abstract: The present invention relates to a flash memory array architecture comprising a plurality of flash memory cells arranged in a NOR type array configuration. Each of the plurality of flash memory cells have a source terminal coupled together to form a common source. The array architecture further comprises a common source selection component coupled between the common source of the array and a predetermined potential. The common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate or float the common source from the predetermined potential in a second state, thereby reducing leakage of non-selected cells associated with the activated bit line during a program mode of operation.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: May 27, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhigang Wang, Nian Yang, Xin Guo
  • Patent number: 6569692
    Abstract: The present invention is directed to an automated method of controlling photoresist develop time to control critical dimensions, and a system for accomplishing same. In one embodiment, the method comprises measuring a critical dimension of each of a plurality of features formed in a layer of photoresist, providing the measured critical dimensions of the features, in the layer of photoresist to a controller that determines, based upon the measured critical dimensions, a duration of a photoresist develop process to be performed on a layer of photoresist formed above a subsequently processed wafer, and performing a photoresist develop process on the subsequently processed wafer for the determined duration.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: May 27, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher A. Bode, Joyce S. Oey Hewett
  • Patent number: 6571371
    Abstract: The present invention provides for a method and an apparatus for using a latency time period as a control input parameter. A manufacturing run of semiconductor devices is processed. Metrology data from the processed semiconductor devices is acquired. A latency analysis process is performed using the acquired metrology data. A feedback/feed-forward modification process is performed in response to the latency analysis process.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: May 27, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Elfido Coss, Jr., Michael R. Conboy, Bryce Hendrix
  • Patent number: 6570157
    Abstract: The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises using a reference having multiple features of different dimensions and spatial interrelationships, wherein more than one feature dimension or spacing is measured using the SEM prior to measuring a workpiece. The dimensional and/or spatial measurements from the reference sample are correlated to obtain one or more calibration factors for the SEM. The calibration factor or factors may then be correlated with a workpiece SEM measurement to obtain a workpiece critical dimension (CD). A system is provided for calibrating a SEM including a reference with various measurable features of different dimensions and/or spacing. The system comprises an SEM to measure one or more reference sample feature dimensions and/or spacings and a processor or other device to correlate the measurement data to obtain one or more calibration factors.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: May 27, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Khoi Phan, Bharath Rangarajan
  • Patent number: 6567718
    Abstract: A method for monitoring consumable performance in a processing tool comprises storing a performance model of the processing tool; receiving a consumable item characteristic of a consumable item in the processing tool; determining a predicted processing rate for the processing tool based on the consumable item characteristic and the performance model; determining an actual processing rate of the processing tool; and determining a replacement interval for the consumable item based on at least the actual processing rate. A processing system includes a processing tool and an automatic process controller. The processing tool is adapted to process wafers and includes a consumable item.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William J. Campbell, Jeremy Lansford, Michael R. Conboy
  • Patent number: 6566886
    Abstract: Various methods of inspecting circuit structures are provided. In one aspect, a method of detecting structural defects in a circuit structure is provided. A natural frequency of the circuit structure is determined and the circuit structure is immersed in a liquid. A first plurality of sonic pulses is sent through the liquid. The first plurality of sonic pulses have a first frequency range selected to produce a plurality of collapsing bubbles proximate the circuit structure. The collapsing bubbles produce a second plurality of sonic pulses that have a second frequency range near or including the natural frequency of the circuit structure whereby the second plurality of sonic pulses causes the circuit structure to resonate. Thereafter, the circuit structure is inspected for structural damage. Early identification of crystalline defects is facilitated.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Terri A. Couteau, Michael J. Satterfield, Laura A. Pressley
  • Patent number: 6566194
    Abstract: The present invention provides processes for doping and saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, word lines are doped prior to patterning the poly layer from which the word lines are formed in the core region. Thereby, the poly layer protects the substrate between the word lines from doping that could cause shorting between bit lines. According to another aspect of the invention, word lines are exposed while spacer material, dielectric, or like material protects the substrate between word lines. The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines even in virtual ground arrays where there are no oxide island isolation regions between bit lines.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark T. Ramsbey, Yu Sun, Chi Chang
  • Patent number: 6567303
    Abstract: A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darlene G. Hamilton, Janet S. Y. Wang, Narbeh Derhacobian, Tim Thurgate, Michael K. Han
  • Patent number: 6566020
    Abstract: A photoresist mask used in the fabrication of an integrated circuit is described. This mask can include a first portion having a phase characteristic; a second portion being located proximate the first portion and having the same phase characteristic as the first portion; and a segment disposed between the first portion and the second portion to prevent phase conflict between the first portion and the second portion.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Hung-Eil Kim
  • Patent number: 6566248
    Abstract: A manufacturing method is provided for an integrated circuit having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core with a random grain texture fills the opening over the barrier layer. The crystallographic orientation of the conductor core is then graphoepitaxially changed to reduce its random grain texture.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin Connie Wang, Minh Quoc Tran
  • Patent number: 6566283
    Abstract: Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a silane plasma produced in a PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a conductive layer within the trench.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Suzette K. Pangrle, Minh Van Ngo, Dawn Hopper, Lu You
  • Patent number: 6567717
    Abstract: When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L2M) and a trim-defined sidewall thickness (SwM), mass production deviations may cause errors between targeted values for these critical dimensions (CD's) and the correspondingly measured CD's. These deviations may respectively cause shifts in the lateral placement of TCI dopants or in the depth of implant of the TCI dopants, thereby tending to cause variation in final device characteristics. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. These countering adjustments in the TCI process enable expansion of tolerance ranges in pre-TCI production steps, thereby increase manufacturing yield.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, William D. Heavlin
  • Patent number: 6566213
    Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William G. En, Srinath Krishnan, Dong-Hyuk Ju, Bin Yu
  • Patent number: 6566655
    Abstract: The present invention provides a system and method that facilitates measuring and imaging topographical features of a substrate, including lines and trenches having reentrant profiles. One aspect of the invention provides an electron microscope that simultaneously scans a substrate with two or more electron beams that are directed against the substrate with substantially differing angles of incidence. Secondary electrons resulting from the interaction of the substrate with the beams are detected by one or more secondary electron detectors. Each secondary electron detector may simultaneously receive secondary electrons resulting from the interaction of the substrate with two or more electron beams. In another of its aspects, the invention provides methods of analysis that permit the interpretation of such data to analyze critical dimensions and form images of the substrate. Critical dimensions that may be determined include feature heights and reentrant profile shapes.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bryan K. Choo, Bhanwar Singh, Sanjay K. Yedur
  • Patent number: 6566176
    Abstract: A transistor device on an SOI wafer includes a metal connect that is in contact with an underside (a bottom surface) of a body of the device. A part of the metal connect is between an active semiconductor region of the device and an underlying buried insulator layer. The metal connect is also in contact with a source of the device, thereby providing some electrical coupling between the source and the body, and as a result reducing or eliminating floating body effects in the device. A method of forming the metal interconnect includes etching away part of the buried insulator layer, for example by lateral etching or isotropic etching, and filling with metal, for example by chemical vapor deposition.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Darin A. Chan
  • Patent number: 6566212
    Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bin Yu, Ming-Ren Lin
  • Patent number: 6567289
    Abstract: The physical layout of a semiconductor memory device having memory sectors of varying sizes can be arranged such that the larger and smaller memory sectors are addressed by x-decoders and y-decoders via word lines and bit lines, respectively. The smaller memory sectors are laid out such that some of the small memory sectors are connected with a y-decoder or multiple y-decoders via different bit-lines. The smaller memory sectors are interspersed with the large memory sectors and an area near a corner of the memory device that can be used for other components such as peripheral devices. Optional physical to logical mapping of address allow the smaller memory sectors to be addressed in the first or the last memory addresses.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lee Cleveland, Yong Kim
  • Patent number: 6566718
    Abstract: A field effect transistor comprises a gate electrode contact of a highly conductive material that contacts the gate electrode and extends in the transistor width dimension at least along a portion of the channel. Thus, the gate resistance and the gate signal propagation time for a voltage applied to the gate contact is significantly reduced even for devices with an extremely down scaled gate length. Moreover, a method for fabricating the above FET is disclosed.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Rolf Stephan, Manfred Horstmann, Stephan Kruegel