Abstract: Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type.

Abstract: A method of making a semiconductor device is provided. A polysilicon layer is formed over a substrate and a metal layer is formed on the polysilicon layer. The metal layer and the polysilicon layer are annealed to form a metal silicide layer on the polysilicon layer. The metal silicide layer is patterned and the polysilicon layer is then patterned using the patterned metal silicide layer as a mask. The patterned metal silicide and polysilicon layers may be used as a gate electrode of a MOSFET.

Abstract: A tunneling junction transistor (TJT) device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The TJT device includes a gate defining a channel interposed between a source and a drain formed within one of the active regions of the SOI substrate. At least one thin nitride layer is interposed between a portion of the channel and at least one of the source and the drain.

Abstract: Moisture seal apparatus and methodologies are disclosed for protecting semiconductor devices from moisture. An upper seal layer, such as SiN is formed over an upper insulator layer and an exposed portion of a die seal metal structure so as to form a vertical moisture seal between electrical components in the semiconductor device and the ambient environment. A lateral seal may be formed from the die seal metal structure in an upper metal layer in the device and one or more contacts extending downward from the die seal metal to the substrate or to a lower die seal metal structure.

Abstract: The present invention is directed to the repair of resistive circuitry in an integrated circuit die having a multitude of circuit paths. According to an example embodiment of the present invention, a semiconductor die having a resistive electrical connection is analyzed. The location of a circuit portion in the die having a resistive electrical connection is identified. Using the identified location, the resistive circuit portion is annealed and the resistivity of that circuit portion is reduced. The reduced resistivity improves the ability of the die to operate at high speeds, and makes possible the repair and subsequent use of the die in various applications.

Abstract: A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask, thereby increasing the width of the substrate under the active areas and increasing Weff for the device.

Abstract: A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.

Abstract: Substrate removal from a semiconductor chip having silicon-on-oxide (SOI) structure is enhanced via a method and system that provide a control for the removal process. According to an example embodiment of the present invention, a portion of substrate is removed from the back side of a semiconductor chip having a SOI structure and a backside opposite a circuit side. As the substrate is removed, secondary ions are sputtered from the back side. The sputtered ions are detected, and the substrate removal is controlled as a function of detected ions. In this manner, the portion of the substrate being removed can be detected and used to enhance the control of the substrate removal process, such as by detecting sputtered ions from the insulating portion of the SOI and using the insulating portion as an endpoint of the substrate removal process.

Abstract: A method for determining operability of a tool includes generating an event log including a plurality of events associated with the operation of the tool; parsing the event log to identify a crucial event; and initiating an automatic corrective action in response to identifying a crucial event. A manufacturing system includes a tool and a tool monitor. The tool is adapted to generate an event log including a plurality of events associated with the operation of the tool. The tool monitor is adapted to parse the event log to identify a crucial event and initiate an automatic corrective action in response to identifying a crucial event.

Abstract: A system for monitoring a latent image exposed in a photo resist during semiconductor manufacture is provided. The system includes one or more light sources, each light source directing light to the latent image and/or one or more gratings exposed on one or more portions of a wafer. Light reflected from the latent image and/or the gratings is collected by a signature system, which processes the collected light. Light passing through the latent image and/or gratings may similarly be collected by the signature system, which processes the collected light. The collected light is analyzed and can be employed to generate feedback information to control the exposure. The collect light is further analyzed and can be employed to generate feed forward information that can be employed to control post exposure processes including development and baking processes.

Abstract: A semiconductor device and a method of making the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a high-K dielectric material and a dielectric precursor material to form a composite layer having at least two sub-layers of at least one of the high-K dielectric material and the dielectric precursor material. The semiconductor device may be subjected to annealing at an elevated temperature to form a composite dielectric layer from the composite layer.

Abstract: A network switch having switch ports for communication of data packets with respective computer network nodes according to CSMA/CD protocol that resets a retry counter for counting data packet transmission attempts within any one of the respective switch ports if backpressure is asserted by that port. A retry limit value for the retry counter is modified to ensure that the total number of retrys does not exceed a maximum total number of allowable retrys. The resetting of the retry counter within a port after assertion of backpressure affords the port a greater probability of transmitting earlier under the CSMA/CD protocol, thus more quickly relieving congestion which may occur in the network switch. The modification of the retry limit value ensures that the number of retrys for the port does not exceed industry standards.

Abstract: A method of manufacturing a semiconductor device includes providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; and forming first and second nickel silicide layer respectively disposed on the source/drain regions and the gate electrode. The nickel silicide layer over the gate electrode can be thicker than the nickel silicide layer over the source/drain regions. A semiconductor device formed from the method is also disclosed.

Abstract: A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties.

Abstract: A system for monitoring and controlling aperture etching in a complimentary phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. Light passing through the apertures may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the depth and/or width of the openings on the mask. The measuring system provides depth and/or width related data to a processor that determines the acceptability of the aperture depth and/or width. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor selectively controls the etching devices so as to regulate aperture etching.

Abstract: A photomask includes a transparent substrate, a line patterning feature having ends formed on the transparent substrate, and an island patterning feature adjacent at least one of the ends of the line patterning feature. A method for fabricating a feature on a wafer includes providing a photomask. The photomask includes a transparent substrate, a line patterning feature having ends formed on the transparent substrate, and an island patterning feature adjacent at least one of the ends of the line patterning feature. A radiation source adapted to supply incident radiation is provided, and a wafer is exposed with the incident radiation through the photomask.

Abstract: A method of manufacturing an integrated circuit which reduces damage to the underlying base layer and the created oxide structures is disclosed herein. The method includes providing a hybrid stack disposed over an underlying layer, providing an IC structure pattern over the hybrid stack, selectively removing the top layer and a portion of the bottom layer according to the IC structure pattern, leaving a protective portion of the bottom layer according to the IC structure pattern, removing the protective portion of the bottom layer, building oxide structures in the underlying layer according to the IC structure pattern, and removing remaining portions of the hybrid stack.

Abstract: A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.

Abstract: A method of using scatterometry measurements to determine and control conductive interconnect profiles is disclosed. In one embodiment, the method comprises providing a library of optical characteristic traces, each of which correspond to a grating structure comprised of a plurality of conductive interconnects having a known profile, providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of conductive interconnects having an unknown profile, and illuminating the formed grating structure. The method further comprises measuring light reflected off of the grating structure to generate an optical characteristic trace for the formed grating structure and determining a profile of the gate electrode structures comprising the formed grating structure by correlating the generated optical characteristic trace to an optical characteristic trace from the library.

Abstract: For fabricating a field effect transistor, a pillar of semiconductor material is formed, a recess is formed in the top surface of the pillar along the length of the pillar, a gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar including at the top surface and the first and second side surfaces of the pillar and at the sidewalls and the bottom wall of the recess, for a gate length along the length of the pillar. In addition, a gate electrode material is deposited on the gate dielectric material to surround the pillar at the top surface and the first and second side surfaces of the pillar and to fill the recess, for the gate length of the pillar.