Abstract: Various integrated circuit voltage regulation apparatus and methods of assembling the same are provided. In one aspect, an apparatus is provided that has a stack that includes a heat sink and a semiconductor chip. The semiconductor chip has a conductive heat transfer pathway to the heat sink. A voltage regulator member is electrically coupled to the semiconductor chip and coupled to the heat sink, but is not positioned in the stack.

Abstract: A method is provided for controlling a data transmission device that includes at least one fractional-sized subdriver. The method includes enabling at least one subdriver and driving a differential signal pair output. Also provided is a device with an output driver having a plurality of subdrivers where at least one subdriver is fractional-sized. The device also includes a de-emphasis portion configured to enable and disable the subdrivers. The device is configured to drive an output data signal. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus such as the device. Also provided is an apparatus that includes an output driver with at least one fractional-sized subdriver and a de-emphasis portion configured to enable and disable the subdrivers of the output driver. The output driver is configured to drive a differential output data signal.

Abstract: A semiconductor product has different active thicknesses of silicon on a single semiconductor substrate. The thickness of the silicon layer is changed either by selectively adding silicon or subtracting silicon from an original layer of silicon. The different active thicknesses are suitable for use in different types of devices, such as diodes and transistors.

Abstract: Various methods of attaching a lid to an integrated circuit substrate are provided. In one aspect, a method of attaching a lid to a substrate that has an integrated circuit positioned thereon is provided. An adhesive is applied to the substrate and an indium film is applied to the integrated circuit. The lid is positioned on the adhesive. The adhesive is partially hardened and the indium film is reflowed. The adhesive is cured.

Abstract: A system, method, and computer program product are provided for improving resource utilization of multithreaded applications. Rather than requiring threads to block while waiting for data from a channel or requiring context switching to minimize blocking, the techniques disclosed herein provide an event-driven approach to launch kernels only when needed to perform operations on channel data, and then terminate in order to free resources. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.

Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.

Abstract: A system includes a plurality of processor cores and a power management unit. The power management unit may be configured to independently control the performance of the processor cores by selecting a respective thermal power limit for each of the plurality of processor cores dependent upon an operating state of each of the processor cores and a relative physical proximity of each processor core to each other processor core. In response to the power management unit detecting that a given processor core is operating above the respective thermal power limit, the power management unit may reduce the performance of the given processor core, and thereby reduce the power consumed by that core.

Abstract: A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.

Abstract: A method, an apparatus, and a non-transitory computer readable medium for performing 2D to 3D conversion are presented. A 2D input source is extracted into left and right 3D images. Motion vectors are calculated for the left and right 3D images. Frame rate conversion is performed on the left 3D image and the right 3D image, using the respective calculated motion vectors, to produce motion compensated left and right 3D images. The left and right 3D images and the motion compensated left and right 3D images are reordered for display.

Abstract: A method and computer program product are provided for resolution enhancement of a video stream based on spatial and temporal correlation. For instance, the method can include predicting interpolated pixels for an image frame of the video stream based on a spatial correlation of pixels in the image frame. The method can also include generating one or more motion vectors for the image frame. Based on the spatially-correlated pixels and the one or more motion vectors, an enhanced image can be reconstructed. Further, the method can include providing a correction factor to one or more pixels in the enhanced image frame.

Abstract: In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems.

Abstract: A decimal floating-point (DFP) adder includes a decimal leading-zero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a leading zero count for the significand. The DFP adder adds or subtracts the DFP operands to obtain a DFP result. The LZA determines the leading zero count associated with the significand of the DFP result. The LZA operates at least partially in parallel with circuitry (in the DFP adder) that computes the DFP result. The LZA does not wait for that circuitry to finish computation of the DFP result. Instead it “anticipates” the number of leading zeros that the result's significand will contain.

Abstract: A secure execution environment for execution of sensitive code and data including a secure asset management unit (SAMU) is described. The SAMU provides a secure execution environment to run multiple instances of separate program code or data code associated with copy protection schemes established for content consumption. The SAMU architecture allows for hardware-based secure boot and memory protection and provides on-demand code execution for multiple instances of separate program code or data provided by a host processor. The SAMU may boot from an encrypted and signed kernel code, and execute encrypted, signed code. The hardware-based security configuration facilitates the prevention of vertical or horizontal privilege violations.

Abstract: A method includes, in a virtualized processing system, generating a local value of a first counter. The local value is accessible while executing in a first mode of the virtualized processing system. The local value is generated based on a value of a second counter and a ratio of a rate of the first counter to a rate of the second counter. The first counter is inaccessible while executing in the first mode of the virtualized processing system and accessible while executing in a second mode of the virtualized processing system. The first mode may be a guest mode and the second mode may be a host mode. The first counter may be an ACPI Power Management Timer. The second counter may be a Time Stamp Counter.

Abstract: An interconnect structure in a semiconductor device may be formed to include a number of segments. Each segment may include a first metal. A barrier structure may be located between the plurality of segments to enable the interconnect structure to avoid electromigration problems.

Abstract: A system and method for controlling communications between a plurality of clients and a central component. An embodiment of the invention includes one or more buses that connect the clients and the central component. This embodiment also includes a control module that is configured to receive ASK messages from the clients and issue GO commands to the clients. Each ASK message represents a request from a client to access the central component. Each GO command to the client represents permission for that client to access the central component. The control module comprises delay stages that delay the GO command. The delays may be different from client to client. The number of delay stages is chosen so that for all clients, the delay between the issuance of a GO command and the receipt at the central component of communications from the clients is the same.

Abstract: A method for determining event based energy weights for digital power estimation includes obtaining a reference energy value corresponding to a power consumed by at least a portion of an integrated circuit (IC) device during operation. The method includes determining and selecting a subset of signals from a set of all signals within the IC that correlates to energy use within the IC. The method includes determining an activity factor of each signal in the subset by monitoring each signal while simulating execution of a particular set of instructions. The method includes determining a weight factor or at least an approximation of a weight factor for each signal in the subset by solving within a predetermined accuracy, a multivariable equation in which the reference energy value equals a weighted sum of the activity of the signals of the selected subset multiplied by their respective weight factors.

Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.

Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.