Abstract: A system, method, and computer program product are provided for tessellation using shaders. New graphics pipeline stages implemented by shaders are introduced, including an inner ring shader, an outer edge shader, and topologic shader, which work together with a domain shader and geometry shader to provide tessellated points and primitives. A hull shader is modified to compute values used by the new shaders to perform tessellation algorithms. This approach provides parallelism and customizability to the presently static tessellation engine implementation.

Abstract: Provided is a method for improving performance of a processor. The method includes computing utilization values of components within the processor and determining a maximum utilization value based upon the computed utilization values. The method also includes comparing (i) the maximum utilization value with a first threshold and (ii) differences between the computed utilization values and a second threshold.

Abstract: Disclosed herein is a vertex core. The vertex core includes a reset scanner configured to remove reset indices and partial primitives in an input stream and resolve draw calls into sub-draw calls at reset index boundaries; and provide the resolved sub-draw calls to a plurality of downstream vertex grouper tessellators.

Abstract: Embodiments for a local data share (LDS) unit are described herein. Embodiments include a co-operative set of threads to load data into shared memory so that the threads can have repeated memory access allowing higher memory bandwidth. In this way, data can be shared between related threads in a cooperative manner by providing a re-use of a locality of data from shared registers. Furthermore, embodiments of the invention allow a cooperative set of threads to fetch data in a partitioned manner so that it is only fetched once into a shared memory that can be repeatedly accessed via a separate low latency path.

Abstract: A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.

Abstract: Provided is a method of testing a logic device. The method includes comparing a first test pattern provided at an input of a first chain of logic device sub-modules with an output from the first chain to determine first type failures and comparing a second test pattern provided at an input of a second chain of logic device sub-modules with an out from the second chain to determine second type failures. An occurrence of one of the first type failures renders the logic device inoperable. An occurrence of the second type of failures is tolerated.

Abstract: Provided is a device including one or more processors, wherein the one or more processors are configured to periodically match an image of an individual with one of a plurality of stored identities based upon at least one from the group including (i) facial print data and (ii) voice print data. The one or more processors are configured to associate the matched image with an icon representative of the one stored identity.

Abstract: Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified.

Abstract: Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product.

Abstract: The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability.

Abstract: A method and apparatus provides for controlling the distribution and installation of operating systems. In one example, the method and apparatus partitions a storage device of a device into a first partition and a second partition. The method and apparatus installs a first operating system into the first partition of the storage device, obtains an image of the second operating system, the image including at least the second operating system pre-configured for operation with the device, and installs, using the first operating system, the image of the operating system to the second partition of the storage device. In an embodiment, the image is transmitted from one or more other devices. In an embodiment, two or more images are cached on the device according to the likelihood they will be used in the future.

Abstract: A method and apparatus for managing a virtual address to physical address translation utilize a subpage level fault detecting and access. The method and apparatus may also use an additional subpage and page store Non-Volatile Store (NVS). The method and apparatus determines whether a page fault occurs or whether a subpage fault occurs to effect an address translation and also operates such that if a subpage fault had occurred, a subpage is loaded corresponding to the fault from a NVS to a DRAM, such as DRAM or any other suitable volatile memory historically referred to as main memory. The method and apparatus, if a page fault has occurred, determines if a page fault has occurred without operating system assistance and is a hardware page fault detection system that loads a page corresponding to the fault from NVS to DRAM.

Abstract: A system and method for creating synthetic immutable classes. A processor identifies first and second classes, instances of which include first and second data fields, respectively. The first data fields include a data field that references the second class. In response to determining that the first class is immutable and the second class is immutable, the processor constructs a first synthetic immutable class, an instance of which comprises a combination of the first data fields and the second data fields. The processor creates an instance of the first synthetic immutable class in which the first data fields and the second data fields occupy a contiguous region of a memory. In response to determining the first synthetic immutable class does not include an accessor for the second class, the processor combines header fields of the first and second data fields into a single data field in the first synthetic immutable class.

Abstract: A method of manufacturing is provided that includes placing a thermal management device in thermal contact with a first semiconductor chip of a semiconductor chip device. The semiconductor chip device includes a first substrate coupled to the first semiconductor chip. The first substrate has a first aperture. At least one of the first semiconductor chip and the thermal management device is at least partially positioned in the first aperture.

Abstract: Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is configured to store a data word, wherein the data word comprises a plurality of bytes of video data. The execution unit is configured to execute a single instruction to (i) shift bytes of video data contained in the data word to align a desired byte of video data and (ii) process the desired byte of the video data to provide processed video data.

Abstract: During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.

Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

Abstract: A method of determining priority within an accelerated processing device is provided. The accelerated processing device includes compute pipeline queues that are processed in accordance with predetermined criteria. The queues are selected based on priority characteristics and the selected queue is processed until a time quantum lapses or a queue having a higher priority becomes available for processing.

Abstract: A method and apparatus is provided for providing local screen data of a source device, such as a personal computer, to a sink device, such as a television, game console, or home theatre system, at a rate determined by the sink device. In one example, the method and apparatus responds to requests from the sink device to provide local screen data by serving the local screen data to the sink device from a circular buffer. The local screen data is written to the circular buffer in FIFO order based on the requests from the sink device, and read from the circular buffer based on the requests.

Abstract: Provided is a method for processing system calls from a GPU to a CPU. The method includes a GPU storing a plurality of tasks in a memory, with each task representing a function to be performed on the CPU. The method also includes generating a CPU interrupt, and processing of the stored plurality of tasks by the CPU.