Patents Assigned to Advanced Micro Devices
  • Patent number: 8463973
    Abstract: A system includes one or more processor cores, and a voltage regulator that provides an operating voltage to the one or more processor cores in response to receiving a voltage identifier signal that is indicative of the operating voltage. The system also includes a power management unit that may provide a first voltage identifier signal corresponding to a first operating voltage in response to determining that the processor cores are operating in a first operating state in which the one or more processor cores may draw up to a maximum load current. The power management unit may also provide a second voltage identifier signal corresponding to a second operating voltage, which is less than the first operating voltage, in response to determining that the processor cores are operating in a second operating state in which the processor cores are incapable of an increase in load current above a predetermined amount.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: June 11, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Samuel D. Naffziger, Alexander Branover
  • Patent number: 8464028
    Abstract: In one embodiment, a processor comprises a redirect unit configured to detect a match of an instruction pointer (IP) in an IP redirect table, the IP corresponding to a guest instruction that the processor has intercepted, wherein the guest is executed under control of a virtual machine monitor (VMM), and wherein the redirect unit is configured to redirect instruction fetching by the processor to a routine identified in the IP redirect table instead of exiting to the VMM in response to the intercept of the guest instruction.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: June 11, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin C. Serebrin, Anton Chernoff
  • Patent number: 8461877
    Abstract: A complementary metal oxide semiconductor (CMOS) circuit is described. The CMOS circuit includes a plurality of CMOS gates, a plurality of logic inputs and a logic output. Each CMOS gate is connected to a negative power supply terminal (Vss) and a positive power supply terminal (Vdd). The CMOS circuit further includes parasitic nets connected to the CMOS gates, and net pulldown circuits for eliminating a charge accumulation on the parasitic nets while avoiding potential short circuit conditions. The CMOS gates may be OR-AND-INVERT (OAI) gates or AND-OR-INVERT (AOI) gates.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: June 11, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kyle S. Viau, James Vinh
  • Patent number: 8461874
    Abstract: A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 11, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dwight K. Elvey, Premlatha Paga
  • Publication number: 20130145202
    Abstract: A method tolerates virtual to physical address translation failures. A translation request is sent from a graphics processing device to a translation mechanism. The translation request is associated with a first wavefront. A fault notification is received within an accelerated processing device (APD) from the translation mechanism that a request cannot be acknowledged. The first wavefront is, stored within a shader core of the APD if the fault notification is received. The first wavefront is replaced with a second wavefront if the fault notification is received, the second wavefront being ready to be executed.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas R. Woller, Sebastien Nussbaum, Rex McCrary, Philip J. Rogers, Mark Leather
  • Publication number: 20130141446
    Abstract: A method, apparatus and computer readable media for servicing page fault exceptions in a accelerated processing device (APD). A page fault related to a wavefront is detected. A fault handling request to a translation mechanism is sent when the page fault is detected. A fault handling response corresponding to the detected page fault from the translation mechanism is received. Confirmation that the detected page fault has been handled through performing page mapping based on the fault handling response is received.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas R. Woller, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Philip J. Rogers, Mark Leather
  • Publication number: 20130141447
    Abstract: A method of accommodating more than one compute input is provided. The method creates an APD arbitration policy that dynamically assigns compute instructions from a sequence of instructions awaiting processing to the APD compute units for execution of a run list.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Mark Leather, Michael Mantor, Rex McCrary, Sebastien Nussbaum, Philip Rogers, Ralph Clay Taylor, Thomas Woller
  • Patent number: 8456194
    Abstract: A level shifter includes first and second input terminals, first and second output terminals, first pull-down circuitry operable to pull down one of the first and second output terminals responsive to signals present on the first and second input terminals, first pull-up circuitry operable to pull up the first output terminal responsive to a signal present on the second output terminal or pull up the second output terminal responsive to a signal present on the first output terminal, and second pull-up circuitry operable to pull up one of the first and second output terminals responsive to the signals present on the first and second input terminals.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: June 4, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael J. Lencioni, Sundararajan Rangarajan
  • Patent number: 8456945
    Abstract: A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: June 4, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Spencer Gold, Stephen V. Kosonocky, Samuel Naffziger
  • Patent number: 8458367
    Abstract: An SMBus message handler, an integrated circuit and a method for controlling an SMBus are disclosed which identifies starting address of a program being stored in a memory. Instructions of the program are fetched one after another into a finite-state machine which controls the data transfer between an SMBus interface and a register set in compliance with the instruction present in the finite-state machine. Further, an SMBus test device and a method for controlling a testing system are described which check as to whether a key is input from a second interface. Upon inputting of a key it is mapped to a sequence of instructions for controlling devices connected to the SMBus or transferring data or receiving data from the devices connected to the SMBus.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 4, 2013
    Assignee: Advanced Micro Devices
    Inventors: René Röllig, Andreas Abt, Frank Schücke, Bernd Schönfelder, Daniel Schöne, Gert Springer
  • Patent number: 8458538
    Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: June 4, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kay Hesse, Suresh Periyacheri
  • Patent number: 8456224
    Abstract: By maintaining a substantially constant total die power during the entire lifetime of sophisticated integrated circuits, the performance degradation may be reduced. Consequently, greatly reduced guard bands for parts classification may be used compared to conventional strategies in which significant performance degradation may occur when the integrated circuits are operated on the basis of a constant supply voltage.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: June 4, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Maciej Wiatr, Richard Heller, Rolf Geilenkeuser
  • Publication number: 20130135327
    Abstract: Provided is a system including a command processor configured for interrupting processing of a first set of instructions executing within a shader core.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Nuwan Jayasena, Mark Leather, Michael Mantor, Rex McCrary, Kevin McGrath, Sebastien Nussbaum, Philip Rogers, Ralph Clay Taylor, Thomas Woller
  • Patent number: 8451064
    Abstract: Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: May 28, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sanjeev Maheshwari, Emerson Fang, Sanjeev Aggarwal
  • Patent number: 8451031
    Abstract: Apparatus and methods are provided for generating output signals representative of bits of serial data. A transmitter includes driver circuitry configured to generate an output signal at an output node and an allocation control module coupled to the driver circuitry. The driver circuitry includes a plurality of driver legs configured to generate the output signal based on a plurality of data bits. The allocation control module is configured to allocate a respective subset of the plurality of driver legs to a respective data bit of a plurality of data bits, wherein the each subset generates a component of the output signal that is influenced by its respective data bit.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: May 28, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Charles Wang, Randall Shaw
  • Patent number: 8451014
    Abstract: A method to test and package dies so as to increase overall yield is provided. The method includes performing a wafer test on a first die and mounting the first die on a package substrate to form a partial package, if the wafer test of the first die is successful. The method further includes performing a system test on the partial package including the first die and stacking a second die on the first die if the system test on the partial package and the first die is successful.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: May 28, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bryan Black, Joseph Siegel
  • Patent number: 8453150
    Abstract: A device may include a memory controller that identifies a multithread application, and adjusts a memory scheduling scheme for the multithread application based on the identification of the multithread application.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: May 28, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jaewoong Chung
  • Publication number: 20130130487
    Abstract: A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
    Type: Application
    Filed: October 4, 2012
    Publication date: May 23, 2013
    Applicants: SPANSION LLC, Advanced Micro Devices, Inc.
    Inventors: Advanced Micro Devices, Inc., SPANSION LLC
  • Patent number: 8446955
    Abstract: A method and apparatus to improve motion prediction in video processing systems is introduced. When a motion prediction cache completes requesting data for a current macroblock and enters an into idle state, data comprising one or more reference frames is speculatively requested, with the hope that the requested data are will be needed in a subsequent macroblock. If the speculative data is needed, then it is consumed. However, if the speculative data is not needed, then the correct data must be requested and a price is paid for an extra memory read bandwidth. In case the speculative data is the correct data for the subsequent macroblock, the effective memory read latency is reduced and the decode performance increases. The video decoder becomes more immune to memory read latency.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 21, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Greg Sadowski, Daniel Wong
  • Patent number: 8447994
    Abstract: One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity than others of the computational units.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: May 21, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sebastien Nussbaum, Alexander Branover, John Kalamatianos