Abstract: A circuit for detecting out-of-band signals is disclosed. In one embodiment, the circuit includes a first differential circuit configured to level shift and positively rectify a differential input signal to produce a first output component of a differential output signal. The first differential circuit is further configured to generate and provide a common mode voltage of the differential input signal as a second component of the differential output signal. The circuit further includes a second differential circuit configured to level shift and output first and second fixed voltages based on an input reference voltage and a ground voltage. The circuit is configured to provide the differential output signal and the first and second fixed voltages to an indicator circuit configured to assert an indication responsive to detecting that a differential voltage of the differential output signal is greater than a differential voltage of the first and second fixed voltages.

Abstract: Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc.

Abstract: The device and accompanying apparatus and method provides security among a calling function, such as an any executable code, and at least one target function, such as any executable code that the calling function wishes to have execute. In one example, the device includes an engine operative to perform run-time verification of the signatures of secure interrupt handler code and at least one target function before allowing execution of the at least one target function. If both the secure interrupt handler code's signature and the at least one target function's signature are successfully verified, the at least one target function is allowed to execute.

Abstract: Dynamic power test slave (DPTS) modules are placed at selected locations of a data processing device to provide data to a logic module of the device at a high rate during testing of the device. The DPTS module intercepts data requests targeted to another logic module and the DPTS instead provides the requested data, thus simulating data transfer by the target logic module. The simulated data transfers can provide for transitions at the data processing device from a relatively high power state to a relatively low power state. Accordingly, the DPTS modules allow for simulation of expected normal operating conditions during testing of the data processing device.

Abstract: In a computing system, memory may be managed by using a distributed array, which is a global set of local memory regions. A segment in the distributed array is allocated and is bound to a physical memory region. The segment is used by a workgroup in a dispatched data parallel kernel, wherein a workgroup includes one or more work items. When the distributed array is declared, parameters of the distributed array may be defined. The parameters may include an indication whether the distributed array is persistent (data written to the distributed array during one parallel dispatch is accessible by work items in a subsequent dispatch) or an indication whether the distributed array is shared (nested kernels may access the distributed array). The segment may be deallocated after it has been used.

Abstract: Data is retrieved from system memory in compressed mode if a determination is made that the memory bus is bandwidth limited and in uncompressed mode if the memory bus is not bandwidth limited. Determination of the existence of the bandwidth limited condition may be based on memory bus utilization or according to a depth of a queue of memory access requests.

Abstract: A system and method for efficient power transfer on a die. A semiconductor chip comprises on a die two or more computation units (CUs) utilizing at least two different voltage regulators and a power manager. The power manager reallocates power credits across the die when it detects an activity level of a given CU is below a given threshold. In response to receiving a corresponding number of donated power credits, each of the one or more selected CUs maintains a high activity level with a high performance P-state. When a corresponding workload increases, each CU maintains operation and an average power consumption corresponding to the high performance P-state by alternating between at least two different operational voltages. When the operational voltage drops during the alternation, the current drawn by the particular CU may exceed a given current limit. The power manager detects this current limit is exceeded and accordingly reallocates the power credits across the die.

Abstract: The deployment of native methods in a virtual machine environment may be significantly simplified by incorporating a corresponding native code segment into the application file, such as a JAVA class file, and using the embedded native code segment for library bind operations of the corresponding class file.

Abstract: A memory device is provided that includes a memory cell, a voltage input, a plurality of bit lines, an amplifier connected to only a particular one of the bit lines, and a switch that is coupled to the amplifier and the voltage input. The switch is configured to prevent the voltage input from being electrically coupled to the amplifier when the plurality of bit lines are electrically floating.

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Abstract: Apparatus and systems utilizing fixed point filtering to perform floating point texture filtering. A texture pipe unit consisting of a texture addressing unit, texture cache unit, and texture filter unit accepts texture requests for a specified pixel from a resource and returns formatted bilinear filtered results based on the specific pixel's corresponding four texels. The texture filtering unit consists of a pre-formatter module, interpolator module, accumulator module and a format module. The pre-formatter module accepts texel data in a floating point or fixed point format. However, if the data is in a floating point format the pre-formatter module converts the floating point data into a normalized fixed point data format whereby the interpolator module may perform its bilinear interpolator functions using standardized fixed point systems and apparatus without necessitating the use of floating point arithmetic units.

Abstract: A method and mechanism for reducing lock time of a dual-path phase lock loop (PLL). The PLL comprises a dual-path low-pass filter (LPF). The LPF includes a first filter and a second filter. The first filter comprises a passive second-order lead-lag low-pass filter. The second filter comprises a first-order lag low-pass filter. During a lock-acquisition state, an impedance value within the second stage is bypassed, which increases the loop bandwidth of the PLL. In addition, a resistance within the first stage is increased in order to increase the gain of the first stage and maintain stability within the PLL. During a lock state, the impedance value may no longer be bypassed and the increased resistance may be returned to its original value.

Abstract: A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.

Abstract: The method and accompanying apparatus and device protects against programming attacks and/or data corruption by computer viruses, malicious code, or other types of corruption. In one example, signature verification policy information that identifies a plurality of policies associated with a plurality of target memory segments is programmed during a secure boot process. The programmed signature verification policy information associated with each of the plurality of target memory segments is then evaluated during run-time. Signature verification is then repeatedly performed, during run-time, on each of the plurality of target memory segments based on the programmed signature verification policy information associated with each target memory segment.

Abstract: A ZIF direct-conversion OFDM receiver capable of estimating and correcting an I/Q imbalance in a baseband signal. A complex down-conversion is performed on a received signal r(t). The received signal r(t) is divided into an In-phase signal (I) and Quadrature-phase signal (Q). An I/Q imbalance is introduced by the local oscillator such that the I/Q imbalance includes an amplitude imbalance factor (?) and phase imbalance factor (?). The I and Q signals are amplified, filtered and digitized. The digitized I and Q signals are processed via a Fast Fourier Transform (FFT). An I/Q compensation algorithm estimates the values of the amplitude imbalance factor (?) and, the phase imbalance factor (?) based on a time expectation calculation. The imbalance factors are applied to the baseband signal to recover the signal of interest x(t). The OFDM receiver outputs the signal of interest x(t) to an information display device.

Abstract: In at least one embodiment of the invention, a method includes scheduling a memory request associated with a thread executing on a processing system. The scheduling is based on a job length of the thread and a priority step function of job length. The thread is one of a plurality of threads executing on the processing system. In at least one embodiment of the method, the priority step function is a function of ?x/2n? for x<=m and P(x)=m/2n for x>m, where x is the number of memory requests in a memory request queue and n and m are integers. In at least one embodiment of the method, the priority step function is a function of 2n×? log2(x)?, where x is the number of memory requests in a memory request queue and n is an integer.

Abstract: Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit.

Abstract: According to one exemplary embodiment, a non-destructive method for determining a breakdown voltage of a dielectric layer on a semiconductor substrate includes injecting a test current in increasing ramp steps into the dielectric layer. The method further includes measuring a test voltage across the dielectric layer at each increasing ramp step of the test current. The method further includes detecting a dropped test voltage in response to the increasing ramp steps of the test current. The ramp steps of the test current can be substantially logarithmically increased. The breakdown voltage of the dielectric layer can be designated to be substantially equal to the dropped test voltage.

Abstract: A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points.

Abstract: A low-hysteresis high-speed latch circuit is disclosed which isolates a sample stage and hold stage from one another during a latch clock phase and simultaneously shorts the output nodes together during the latch clock phase to reduce hysteresis of the latch.