Abstract: In a polishing process, the characteristics of the removal process may be monitored at different lateral positions to identify the clearance of the various device regions with a high degree of reliability. Consequently, upon forming sophisticated metallization structures, undue over-polishing may be avoided while at the same time providing reduced leakage currents due to enhanced material removal.
Abstract: Apparatus and methods for a bilinear filter system comprising a pre-formatter module, a bilinear module, an accumulator module, and a format module. The pre-formatter module is configured to receive texel data and convert it to a normalized fixed point format. The bilinear module is dynamically reconfigurable to perform an interpolation or an extended precision interpolation on the normalized fixed point texel data from the pre-formatter module and generate re-normalized floating point texel data. The interpolator analyzes the exponent range of fixed point texel data from the pre-formatter module to determine if an extended precision calculation is appropriate. The accumulator module is configured to accumulate floating point texel data from the bilinear module to achieve the desired level of bilinear, trilinear, and anisotropic filtering. The format module is configured to convert texel data from the accumulator module into a standard floating point representation.
Abstract: Photolithography methods using BARCs having graded optical properties are provided. In an exemplary embodiment, a photolithography method comprises the steps of depositing a BARC overlying a material to be patterned, the BARC having a refractive index and an absorbance. The BARC is modified such that, after the step of modifying, values of the refractive index and the absorbance are graded from first values at a first surface of the BARC to second values at a second surface of the BARC. The step of modifying is performed after the step of depositing.
Abstract: During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.
Type:
Grant
Filed:
February 24, 2010
Date of Patent:
April 10, 2012
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Oliver Aubel, Joerg Hohage, Frank Feustel, Axel Preusse
Abstract: A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The system and method are applicable to any processor in which multiple threads require access to sets of state information which differ from one another by a relatively small number of state changes.
Abstract: A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver.
Abstract: The present disclosure generally addresses the problem of controlling a plating profile in multi-step recipes and addresses, in particular, the problem of compensating for variations of the plating tool state to stabilize the plating results. The compensation is done by adjustments of corrections factors for currents of a plating tool in a multi-anode configuration. The described method enables control of recipes with different current ratios in each recipe step and models different deposition sensitivities in each recipe step. Generally, the method of the present disclosure requires a measurement step, where the tool state is determined, and a data processing step, where the correction factors are set based on models describing the plating process and the tool state.
Abstract: A method for monitoring a photolithography system includes defining a model of the photolithography system for modeling top and bottom critical dimension data associated with features formed by the photolithography system as a function of dose and focus. A library of model inversions is generated for different combinations of top and bottom critical dimension values. Each entry in the library specifies a dose value and a focus value associated with a particular combination of top and bottom critical dimension values. A top critical dimension measurement and a bottom critical dimension measurement of a feature formed by the photolithography system using a commanded dose parameter and a commanded focus parameter are received. The library is accessed using the top and bottom critical dimension measurements to generate values for a received dose parameter and the received focus parameter.
Type:
Grant
Filed:
December 17, 2007
Date of Patent:
April 3, 2012
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Siddharth Chauhan, Kevin R. Lensing, James Broc Stirton
Abstract: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
Type:
Grant
Filed:
October 10, 2006
Date of Patent:
March 27, 2012
Assignees:
Spansion LLC, Advanced Micro Devices, Inc.
Abstract: A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first TLB, the physical address is requested from a set of page tables. When the data processing device is in a hypervisor mode, a second TLB is accessed in response to the request to access the page tables. If the virtual address is located in the second TLB, the hypervisor page tables are bypassed and the second TLB provides a physical address or information to access another table in the set of page tables. By bypassing the hypervisor page tables, the time to translate an address in the hypervisor mode is reduced, thereby improving the efficiency of the data processing device.
Abstract: A method of receiving communications at a data processing device includes receiving a packet from a virtual channel associated with a physical communication link. The packet is associated with a link virtual channel, and is stored in a storage location with the link virtual channel. Multiple internal virtual channels can be associated with the link virtual channel. A pointer to the storage location is enqueued in one of a plurality of FIFOs associated with one of the internal virtual channels. Each FIFO of the plurality of FIFOs stores pointers associated with a different internal virtual channel, allowing receiver arbitration logic to reorder between internal virtual channels based on internal resource availability and current priorities among virtual channels. This reduces the likelihood of communication deadlock and supports multiple classes of service.
Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region.
Type:
Grant
Filed:
November 23, 2009
Date of Patent:
March 27, 2012
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Jan Hoentschel, Thomas Feudel, Ralf Illgen
Abstract: In one aspect, there is provided a video decoder including a first write port to write uncompressed video data to a first buffer in a first format adapted based on an input required by the video decoder and to suppress writing to the first buffer. The video decoder also includes a second write port to write uncompressed video data to a second buffer in a second format adapted to provide the uncompressed video data for subsequent processing external to the video decoder.
Type:
Grant
Filed:
May 25, 2007
Date of Patent:
March 20, 2012
Assignees:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
Greg Sadowski, Wai Ki Lo, Haibo Liu, Stephen Edward Smith, Thomas E. Ryan
Abstract: Methods and apparatus, including computer program products, are provided for channel estimation. In one aspect, there is provided a receiver including a demodulator for decoding a signal including at least one of a transmission parameter signaling (TPS) carrier and a data carrier. The receiver further includes a channel estimator, coupled to the demodulator, for determining a channel estimate for the TPS carrier. Moreover, the receiver includes an interpolator, coupled to the channel estimator, for determining, based on the determined channel estimate for the TPS carrier, another channel estimate for the data carrier. Related systems, methods, and articles of manufacture are also disclosed.
Abstract: A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.
Abstract: A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request.
Type:
Grant
Filed:
December 5, 2007
Date of Patent:
March 13, 2012
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Brian Etscheid, Mark S. Grossman, Warren Fritz Kruger
Abstract: A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.
Type:
Grant
Filed:
June 10, 2010
Date of Patent:
March 13, 2012
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Meei-Ling Chiang, Dennis M. Fischette, Alvin Leng Sun Loke, Michael M. Oshima
Abstract: A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.
Type:
Grant
Filed:
March 20, 2007
Date of Patent:
March 13, 2012
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Michael John Haertel, R. Stephen Polzin, Andrej Kocev, Maurice Bennet Steinman
Abstract: By providing a look-ahead functionality for a tool internal substrate handling system of process tools on the basis of a process history, the tool internal substrate sequencing may be significantly enhanced. The look-ahead functionality enables a prediction of process time of substrates currently being processed in a respective process module, thereby enabling the initiation of transport activity for substrate load operations in order to significantly reduce the overall idle time of process modules occurring during substrate exchange.
Abstract: An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.
Type:
Grant
Filed:
November 30, 2009
Date of Patent:
February 28, 2012
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin Pohlack