Abstract: A high yield plasma etch process for an interlayer dielectric layer of a semiconductor device is provided, according to an embodiment of which a dielectric layer is etched with a nitrogen-containing plasma. In this way, the formation of polymers on a backside bevel of a substrate is avoided or substantially reduced. Remaining polymer at the backside bevel can be removed in situ by post-etch treatment. Further, a plasma etching device is provided comprising a chamber, a substrate receiving space for receiving a substrate, a plasma generator for generating a plasma in the chamber and a temperature conditioner for conditioning a temperature at an outer circumferential region of the substrate receiving space and thereby minimizing temperature gradients at a bevel of the wafer.

Abstract: A multi-core microprocessor provides an indication of the power management state of each of the cores on output terminals. Cooling of the cores is adjusted responsive to the indication of the power management state of the respective cores with additional cooling being provided to those cores in a more active state and less cooling provided to those cores in a less active state.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.

Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.

Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Abstract: By forming an appropriate material layer, such as a metal-containing material, on a appropriate substrate and patterning the material layer to obtain a cantilever portion and a tip portion, a specifically designed nano-probe may be provided. In some illustrative aspects, additionally, a three-dimensional template structure may be provided prior to the deposition of the probe material, thereby enabling the definition of sophisticated tip portions on the basis of lithography, wherein, alternatively or additionally, other material removal processes with high spatial resolution, such as FIB techniques, may be used for defining nano-probes, which may be used for electric interaction, highly resolved temperature measurements and the like. Thus, sophisticated measurement techniques may be established for advanced thermal scanning, strain measurement techniques and the like, in which a thermal and/or electrical interaction with the surface under consideration is required.

Abstract: Embodiments of a method for detecting potential areas of inductive coupling in a high density integrated circuit design are described. The inductance mitigation process first converts the inductive analysis into a density problem. The density of wires within a region that may switch within a portion of the system clock are compared to the density of wires will not switch within that same time. Regions of the chip that have a high ratio of density of switching wires versus non-switching wires are determined to have the potential of an inductive coupling problem. Additional grounded metal is added into the problematic regions of the chip to improve the switching versus non-switching wire density.

Abstract: Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.

Abstract: A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.

Abstract: In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt message communicating a first interrupt that is targeted at a host in the system. The second interrupt controller is configured to signal the processor for an interrupt in response to receiving a second interrupt message communicating a second interrupt that is targeted at a guest that is controlled by the host and that is executable on the processor.

Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

Abstract: A memory system (250) includes a plurality of memory devices (260) adapted to be coupled to an interface (140), an indicator (272) for indicating a type of the plurality of memory devices (260), and an override circuit (280) having a first terminal adapted to be coupled to the interface (140), a second terminal coupled to the plurality of the memory devices (260), and a control input for receiving a control signal. The override circuit (280) is responsive to the control signal to alter an operation of the memory system (250).

Abstract: A method of estimating a time variant Orthogonal Frequency Division Multiplexing (OFDM) while eliminating Inter-carrier Interference (ICI) is disclosed, where the time variant channel matrix is estimated at channel taps using a Basis Expansion Model (BEM). The BEM method decomposes the time variant channel into a group of basis functions in the frequency domain. Coefficients are estimated using a sub-space tracking algorithm that decreases the dimensions of the coefficient matrix allowing for simpler calculation of the estimated signal. The coefficients matrix is estimated using a conjugate gradient iterative method that may be stopped after 6-8 iterations to arrive at an acceptable estimation. Finally, the transmitted data is estimated, again using the conjugate gradient method iteratively, wherein the conjugate gradient method is stopped after a small number of iterations.

Abstract: A method includes establishing a first link between a first processor device and a first memory module at a first time. A second link is established between a second processor device and a second memory module at a second time. In response to receiving a first event indicator, a third link is established between the first processor device and the second memory module at a third time, the third time after the first time and the second time.

Abstract: A method for determining parking assignments for material handling vehicles in a manufacturing system is provided. The manufacturing system is operable to perform fabrication processes on a plurality of loads. The method includes identifying at least one idle material handling vehicle. A first cost factor associated with expected transit times for the at least one idle material handling vehicle to available parking locations in the manufacturing system is determined. A second cost factor based on a number of loads available to be serviced by the at least one idle material handling vehicle in the parking locations and relative priorities assigned to the loads is determined. A parking location for the at least one idle material handling vehicles is determined based on the first and second cost factors. A parking request is issued to the at least one idle material handling vehicle based on the determined parking locations.

Abstract: By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree of etch selectivity during the patterning of openings in a metallization layer of a semiconductor device.

Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Abstract: A method includes defining a general query for extracting data from at least one data store operable to store workpiece data associated with the processing of workpieces in a manufacturing system. The general query specifies at least one ambiguous parameter having a plurality of potential values. Metadata associated with the workpiece data is accessed. The metadata is employed to identify a plurality of candidate values for the at least one ambiguous parameter. A plurality of atomic queries is generated. Each atomic query is associated with one of the candidate values. The plurality of atomic queries is executed to extract data from the at least one data store and generate an output report including the extracted data.