Abstract: A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a plurality of memory pages. The MMU includes a security check unit (SCU) receiving a linear address generated during execution of a current instruction. The linear address has a corresponding physical address residing within a selected memory page. The SCU uses the linear address to access one or more security attribute data structures located in the memory to obtain a security attribute of the selected memory page. The SCU compares a numerical value conveyed by a security attribute of the current instruction to a numerical value conveyed by the security attribute of the selected memory page, and produces an output signal dependent upon a result of the comparison. The MMU accesses the selected memory page dependent upon the output signal.
Type:
Grant
Filed:
November 13, 2001
Date of Patent:
November 1, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Brian C. Barnes, Geoffrey S. Strongin, Rodney W. Schmidt
Abstract: An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.
Abstract: A method includes providing a design data file specifying at least one target feature on a first reticle. A reticle qualification data file specifying a plurality of feature measurements associated with features formed using the first reticle is provided. At least one of the feature measurements is linked to the target feature on the first reticle. The target feature and the linked feature measurement are stored in a data store.
Abstract: By forming metal capacitors in the metallization structures of semiconductor devices, complex manufacturing sequences in the device level may be avoided. The process of manufacturing the metal capacitors may be performed on the basis of well-established patterning regimes of modern metallization systems by using appropriately selected etch stop materials, which may enable a high degree of compatibility for forming via openings in a metallization layer while providing a capacitor dielectric of a desired high dielectric constant in the capacitor.
Type:
Grant
Filed:
July 15, 2008
Date of Patent:
November 1, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Thomas Werner, Frank Feustel, Kai Frohberg
Abstract: A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar transistor is provided that has a collector, a base and an emitter. The body region of the MOS transistor serves as the base of the bipolar transistor and the drain region of the MOS transistor serves as the collector of the bipolar transistor. Activation of the MOS transistor causes the bipolar transistor to turn on. The MOS transistor is activated to turn on the bipolar transistor and the bipolar transistor delivers current to the source region.
Abstract: A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.
Type:
Grant
Filed:
February 25, 2009
Date of Patent:
November 1, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Ruigang Li, David Donggang Wu, James F. Buller, Jingrong Zhou
Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
Type:
Grant
Filed:
May 19, 2009
Date of Patent:
November 1, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.
Abstract: A transaction is sent over a communication link to a receiving node. The transaction includes data along with a tag identifying a data type of the data. The receiving node either forwards or processes the data according to whether the data type matches the type of data type processed by circuitry associated with the receiving node. Thus, a destination is determined for data transported on the communication link using a data type identifier sent with the data.
Type:
Grant
Filed:
March 29, 2002
Date of Patent:
October 25, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Evandro Menezes, Dave Tobias, Morrie Altmejd
Abstract: A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device.
Abstract: By taking into consideration the combination of the substrate holders in various lithography tools used during the imaging to two subsequent device layers, enhanced alignment accuracy may be accomplished. Furthermore, restrictive tool dedications for critical lithography processes may be significantly relaxed by providing specific overlay correction data for each possible process flow, wherein, in some illustrative embodiments, a restriction of the number of possible process flows may be accomplished by implementing a rule for selecting a predefined substrate holder when starting the processing of an associated group of substrates.
Abstract: In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar.
Type:
Grant
Filed:
October 8, 2009
Date of Patent:
October 18, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Alexander Platz, Matthias Lehr, Frank Kuechenmeister
Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
Type:
Grant
Filed:
January 13, 2011
Date of Patent:
October 18, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Sven Beyer, Manfred Horstmann, Patrick Press, Wolfgang Buchholtz
Abstract: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.
Type:
Grant
Filed:
June 23, 2010
Date of Patent:
October 18, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Igor Peidous, Thorsten Kammler, Andy Wei
Abstract: Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.
Type:
Grant
Filed:
March 18, 2009
Date of Patent:
October 11, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Maxat Touzelbaev, Gamal Refai-Ahmed, Yizhang Yang, Bryan Black
Abstract: Methods and systems for processing memory lookup requests are provided. In an embodiment, an address processing unit includes an instructions module configured to store instructions to be executed to complete a primary memory lookup request and a logic unit coupled to the instructions module. The primary memory lookup request is associated with a desired address. Based on an instruction stored in the instructions module, the logic unit is configured to generate a secondary memory lookup request that requests the desired address. In another embodiment, a method of processing memory lookups requests includes receiving a primary memory lookup request that corresponds to a desired memory address and generating a plurality of secondary memory lookup requests.
Abstract: A scannable flop circuit configured for operation in a multiple modes. The scannable flop circuit includes a functional flop having a data input, a clock input, and a data output, a scan flop having a scan data input and a scan data output, and a latch circuit coupled between the functional flop and the scan flop. The latch circuit includes one or more mode signal inputs to enable selection of an operating mode. In a first mode, the latch circuit is configured to enable the functional flop to provide a data signal to the scan flop. In a second mode, the latch circuit is configured to enable the scan flop to provide a data signal to the functional flop. In a third mode, the latch circuit is configured to provide a feedback path in order to feed back to the functional flop a signal generated by the functional flop.
Abstract: By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.
Type:
Grant
Filed:
July 1, 2008
Date of Patent:
October 11, 2011
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Ralf Richter, Michael Finken, Joerg Hohage, Heike Salz
Abstract: Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests sent to an L2 cache are flushed during a context switch. Such a system may include a work queue and a cache (such as an L2 cache). The work queue comprises a plurality of state machines, each configured to store a request for access to memory. The state machines can monitor requests that are stored in the other state machines and requests that the other state machines issue to the cache. A state machine only sends its request to the cache if another state machine is not already awaiting translation data relating to the that request. In this way, the request/translation traffic between the work queue and the cache can be significantly reduced.
Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.