Abstract: A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material.

Abstract: By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin hydride and nickel, carbon monoxide in a thermally driven reaction.

Abstract: Various die crack deflection structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a semiconductor chip including an outer edge, a first side and a second side opposite to the first side. A deflection structure is fabricated in the semiconductor chip. The deflection structure includes a sloped profile to deflect a crack propagating in the semiconductor chip toward the first side or the second side of the semiconductor chip.

Abstract: By locally heating specific scan positions within a region of interest and automatically obtaining respective measurement data in a time-resolved and spatially-resolved fashion, dynamic processes within a metallization layer of semiconductor devices may be efficiently monitored and/or modified. For instance, OBIRCH and SEI techniques may be used in combination with the automated data recording and manipulation, thereby providing an efficient means for in situ failure analysis, defect identification, for any dynamic degradation processes in interconnects and interlayer dielectrics.

Abstract: By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified.

Abstract: Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

Abstract: A processor core includes one or more cache memories and a repair unit. The repair unit may repair locations in the cache memories identified as having errors during an initialization sequence. The repair unit may further cause information corresponding to the repair locations to be stored within one or more storages. In response to initiation of a power-down state of a given processor core, the given processor core may execute microcode instructions that cause the information from the one or more storages to be saved to a memory unit. During a recovery of the given processor core from the power-down state, the processor core may execute additional microcode instructions that cause the information to be retrieved from the memory unit, and saved to the one or more storages. The repair unit may restore repairs to the locations in the cache memories using the information.

Abstract: By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the strain-inducing region may be incorporated at an early manufacturing stage, directly to respective “large area” contact elements.

Abstract: When forming sophisticated metallization systems, surface integrity of an exposed metal surface, such as a copper-containing surface, may be enhanced by exposing the surface to a vapor of a passivation agent. Due to the corresponding interaction with the metal surface, enhanced integrity may be accomplished, while at the same time damage of exposed dielectric surface portions may be significantly reduced compared to conventional aggressive wet chemical cleaning processes that are typically used in conventional patterning regimes.

Abstract: An integrated fin-based field effect transistor (FinFET) and method of fabricating such devices on a bulk wafer with EPI-defined fin heights over shallow trench isolation (STI) regions. The FinFET channels overlie the STI regions within the semiconductor bulk, while the fins extend beyond the STI regions into the source and drain regions which are implanted within the semiconductor bulk. With bulk source and drain regions, reduced external FinFET resistance is provided, and with the fins extending into the bulk source and drain regions, improved thermal properties is provided over conventional silicon on insulator (SOI) devices.

Abstract: According to one exemplary embodiment, a method for determining a self-heating free drain current in a transistor corresponding to a channel temperature not affected by a drain DC current includes measuring at least three unique drain currents of a transistor corresponding to at least three unique ambient temperatures. The method further includes determining at least three unique channel temperatures of the transistor corresponding to the at least three unique drain currents, thereby establishing a current-temperature relationship for the transistor. The method further includes determining the self-heating free drain current of the transistor utilizing the current-temperature relationship.

Abstract: A method for managing work distribution in a processor including a plurality of instruction data modules, is provided. The method includes analyzing work units received by the processor and comparing the utilization level in each active module within the plurality with a first predetermined threshold. The work units are distributed across selected ones of the modules within the plurality based upon the analyzing and the comparing.

Abstract: Disclosed herein is a vertex core. The vertex core includes a grouper module configured to process two or more primitives during one clock period and two or more vertex translators configured to respectively receive the two or more processed primitives in parallel.

Abstract: Various embodiments of systems and methods for dynamically reallocating buffers used in communicating packets in various communication channels are disclosed. In some embodiments, a method may involve transmitting packets in several communication channels dependent on availability of buffers allocated among the communication channels; tracking a history of packet traffic in each of the communication channels; and dynamically reallocating one or more of the buffers dependent on the history.

Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices.

Abstract: During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabilities of subsequent metal deposition processes. In one particular embodiment, an additional etch process is performed after etching through the capping layer and the low-k dielectric layer and after resist removal.

Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.

Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.

Abstract: An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate.

Abstract: Systems and methods to improve performance in a graphics processing unit are described herein. Embodiments achieve power saving in a graphics processing unit by dynamically activating/deactivating individual SIMDs in a shader complex that comprises multiple SIMD units. On-the-fly dynamic disabling and enabling of individual SIMDs provides flexibility in achieving a required performance and power level for a given processing application. Embodiments of the invention also achieve dynamic medium grain clock gating of SIMDs in a shader complex. Embodiments reduce switching power by shutting down clock trees to unused logic by providing a clock on demand mechanism. In this way, embodiments enhance clock gating to save more switching power for the duration of time when SIMDs are idle (or assigned no work). Embodiments can also save leakage power by power gating SIMDs for a duration when SIMDs are idle for an extended period of time.