Patents Assigned to Advanced Micro Devices
  • Determining metrology sampling decisions based on fabrication simulation
    Patent number: 7257502
    Abstract: A method for determining metrology sampling rates for workpieces in a process flow includes determining a current status of the process flow. Future processing of the workpieces in the process flow is simulated based on the current status of the process flow over a predetermined time horizon to predict sampling rates for the workpieces. During the simulating, sampling rules are implemented that consider capacity constraints of a metrology resource in the process flow. Actual workpieces in the process flow are sampled based on the predicted metrology sampling rates.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: August 14, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Peng Qu, Chandrashekar Krishnaswamy
  • Selective P-channel Vadjustment in SiGe system for leakage optimization
    Patent number: 7253045
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon germanium layer and a N-channel transistor and a P-channel transistor over the silicon germanium layer. A beta ratio of the N-channel transistor to the P-channel transistor is about 1.8 to about 2.2. A semiconductor device is also disclosed.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Derick J. Wristers, David Wu, Hormuzdiar E. Nariman
  • Testing for operating life of a memory device with address cycling using a gray code sequence
    Patent number: 7254692
    Abstract: In a method and system for cycling through addresses of a memory device, a respective bit pattern comprised of a predetermined number of bits is generated for each address. The respective bit pattern for each of the addresses is cycled through with a transition of less than the predetermined number of bits for sequencing to each subsequent address. For example, the respective bit pattern for each of the addresses is cycled through in a gray code sequence. By limiting the number of transitions in the address bits, charge gain failure of a flash memory device is minimized and even may be eliminated.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wan Yen Teoh, Che Seong Law
  • Active programming and operation of a memory device
    Patent number: 7254053
    Abstract: Systems and methodologies for programming a memory cell having a functional or selective conductive layer are provided. The functional zone can include active, and/or passive and/or barrier layers. The system includes a controller that can actively trace conditions associated with such programming. In one aspect of the present invention, by providing an external stimulus, an associated electrical or optical property associated with the memory cell is affected. Such property is then compared to a predetermined value to set/verify a programming state for the memory cell. The external stimulus can then be removed upon completion of the programming, or reduced to a verifying state to read information. The memory cell can include alternating layers of active, passive, diode, and barrier layers positioned between at least two electrodes.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Juri Heinrich Krieger, Nikolay Fedorovich Yudanov
  • Method and system for testing a memory of a microprocessor
    Patent number: 7254509
    Abstract: In one embodiment, a method may include generating a test code segment including a number of selected opcodes and executing the test code segment from a particular location within the memory for a first iteration. The method may also include saving a first test result of the execution of the test code segment after the first iteration. In addition, the method may include executing the test code segment for subsequent iterations and after each iteration of the test code segment, shifting the test code segment a predetermined number of locations from the particular location within the memory. The method may further include comparing test results of each subsequent iteration with the first test result and determining whether any of the subsequent test results are different than the first test result.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Trent W. Johnson
  • System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit
    Patent number: 7254721
    Abstract: A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David F. Tobias, Evandro Menezes, Richard Russell, Morrie Altmejd
  • Secondary process controller for supplementing a primary process controller
    Patent number: 7254453
    Abstract: A method and an apparatus for implementing a multi-variate process control system. A workpiece is processed using a primary process control function during a first time period. A secondary process control function is performed during at least a portion of the first time period for processing of the workpiece. The secondary process control function is capable of modifying at least one secondary control parameter.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Markle, Thomas J. Sonderman
  • Split-transaction bus intelligent logic analysis tool
    Patent number: 7254115
    Abstract: An improved split-transaction bus intelligent logic analysis tool has a bus synchronizer, a decoder and a logic analysis function. The bus synchronizer is configured to receive link traffic and frame the link traffic into a plurality of framed packets, the plurality of framed packets including a plurality of request packets and a plurality of response packets. The decoder is configured to receive the plurality of framed packets and decode the plurality of framed packets into decoded packets, wherein at least one of the decoded packets includes information from a request packet and information from a corresponding response packet. The logic analysis function is configured to receive the decoded packets and initiate a trigger action on receipt of one of the decoded packets.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sanjiv K. Lakhanpal, Steven R. Klassen, Mark D. Nicol
  • Integrated circuit package and method
    Patent number: 7253504
    Abstract: An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configured to resist warpage of the integrated circuit package, the layer provided a distance from the central axis.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jun Zhai, Jinsu Kwon, Richard C. Blish, II
  • Dual SOI film thickness for body resistance control
    Patent number: 7253068
    Abstract: The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dong-Hyuk Ju, Srinath Krishnan, Mario Pelella
  • Low-power multiple-channel fully depleted quantum well CMOSFETs
    Patent number: 7253484
    Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James N. Pan, John G. Pellerin, Jon Cheek
  • Multi-processor task scheduling
    Patent number: 7254812
    Abstract: An information processing system is configured to schedule tasks to a plurality of processors using processor performance information. For example, the maximum performance level of each of the processors, the current performance level of each of the processors, and the number of processors can be used to schedule tasks to one or more of the processors. A task distribution frequency which takes this information into account can be useful. One such task distribution frequency fi is calculated so that fi=Di/?Di where i ranges from 1-N and Di=MPi/CPi/N, where MPi is a maximum performance level for the processor i, CPi is a current performance level for the processor i, and N is the number of processors. Tasks are distributed according to the task distribution frequency fi.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Evandro Menezes
  • Reversed T-shaped FinFET
    Patent number: 7250645
    Abstract: A fin field effect transistor (FinFET) includes a reversed T-shaped fin. The FinFET further includes source and drain regions formed adjacent the reversed T-shaped fin. The FinFET further includes a dielectric layer formed adjacent surfaces of the fin and a gate formed adjacent the dielectric layer.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Haihong Wang, Shibly S. Ahmed, Ming-Ren Lin, Bin Yu
  • Selectable open circuit and anti-fuse element
    Patent number: 7250667
    Abstract: An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darin A. Chan, Simon Siu-Sing Chan, Paul L. King
  • Cache memory subsystem including a fixed latency R/W pipeline
    Patent number: 7251710
    Abstract: A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule reads and writes of information associated with the cache storage using a fixed latency pipeline. In response to scheduling a read request, the scheduler may be further configured to cause an associated write to occur a fixed number of cycles after the scheduling of the read request.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Roger D. Isaac, Mitchell Alsup, Rama S. Gopal, James K. Pickett, Michael A. Filippo
  • Memory check architecture and method for a multiprocessor computer system
    Patent number: 7251744
    Abstract: Methods and apparatus are provided for use in testing a memory (220, 230, 240) in a multiprocessor computer system (200). The multiprocessor computer system (200) has a plurality of processing nodes (210-217) coupled in an array wherein each processing node is coupled to at least one other processing node, and a memory (220, 230, 240) distributed among the plurality of processing nodes (210-217). A configuration of the array is determined. An initial configuration of the memory (220, 230, 240) is also determined. The memory (220, 230, 240) is tested over the array according to the initial configuration to identify a bad memory element. The initial configuration is modified to form a revised configuration that excludes the bad memory element.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices Inc.
    Inventor: Oswin Housty
  • Minimum equalization error based channel estimator
    Patent number: 7251273
    Abstract: A channel estimator, configured for supplying equalization coefficients to a frequency equalizer, is configured for determining equalizer coefficients for a received wireless signal based on a minimum equalization error-based estimation. The channel estimator is configured for identifying first and second long preambles from the received wireless signal, determining an equalization coefficient for a selected frequency based on a minimized cost function for the first and second long preambles relative to a prescribed preamble value for the selected frequency, and supplying the equalization coefficient for the selected frequency to a frequency equalizer for equalization of the received wireless signal.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chien-Meen Hwang, Ping Hou, Jia-Pei Shen
  • In-situ reticle contamination detection system at exposure wavelength
    Patent number: 7251033
    Abstract: A system and method are provided for detecting contaminants or defects on a reticle in-situ. The system and method provide a system that measures the optical transmission through clear areas on a reticle and determines whether the optical transmission of a reticle has been degraded by contaminants or other defects.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
  • Predicting defect future effects in integrated circuit technology development to facilitate semiconductor wafer lot disposition
    Patent number: 7251793
    Abstract: A method for facilitating semiconductor wafer lot disposition includes providing detailed descriptive information of the semiconductor wafer layout and generating data concerning at least one defect in the semiconductor wafers at an intermediate processing stage. At least one layer model is generated from the information and data to disclose the effects of the defect upon at least one later layer of the semiconductor wafers. The layer model is utilized to determine the subsequent disposition of the wafer lot.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul J. Steffan
  • Viterbi decoder utilizing partial backtracing
    Patent number: 7248637
    Abstract: A Viterbi decoder is configured for outputting a prescribed plural number of decoded bit pairs upon execution of each backtracing operation based on accessing a second prescribed number of state history table entries from a surviving state history table. The outputting of more bits per backtrace operation lowers the number of memory accesses, and enables the Viterbi decoder to maintain a high throughput of data flow while maintaining an acceptable bit error rate.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: July 24, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chien-Meen Hwang, Christine Lee, Howard Hicks