Abstract: A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.

Abstract: A method for forming an inlaid interconnect structure for ICs. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a dielectric layer and cap layer over the etch stop layer, forming a photoresist pattern, and etching the cap and dielectric to form an opening that is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The dielectric layer and cap layers are then deposited over both regions and two via or trench openings are formed therethrough in the regions, respectively.

Abstract: A method and apparatus for managing recipes in a semiconductor manufacturing process. Recipes and associated process contexts in a manufacturing execution system and corresponding recipes and associated contexts in a recipe management system are audited to identify discrepancies. The discrepancies are reconciled to ensure that compatible recipes and process contexts are maintained in the manufacturing execution system and the recipe management system. The audit and reconciliation process can be initiated automatically at predetermined time intervals or can be initiated interactively by a user of the manufacturing system.

Abstract: By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.

Abstract: In one embodiment, the present invention relates to a method for increasing the ignition reliability of a plasma in a plasma reactor, the method comprising: supplying a source gas to the plasma reactor, the source gas comprising: (a) at least one reactive compound; and (b) at least one ignition gas, wherein the at least one ignition gas increases the ignitability of the source gas as compared to the ignitability of the source gas lacking the at least one ignition gas.

Abstract: A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.

Abstract: A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters enter a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.

Abstract: The present invention provides a method and apparatus for classifying faults. The method includes accessing wafer state data associated with at least one wafer processed by at least one processing tool and sensor tool trace data associated with the at least one processing tool and determining that at least one fault occurred based upon at least one of the wafer state data and the sensor tool trace data. The method also includes selecting, in response to determining that the at least one fault occurred, a subset of a plurality of faults based upon at least one of the wafer state data and the sensor tool trace data and selecting at least one fault from the subset of the plurality of faults based upon at least one of the wafer state data and the sensor tool trace data.

Abstract: A device that transmits data using discrete multitone modulation includes a memory that stores intercarrier interference (ICI) information for each of the tones used to transmit data. The device also includes logic that receives signals transmitted from another device, estimates a noise value for each tone and adds the estimated noise to the ICI information to determine an effective noise value. The effective noise value may then be used to generate an effective signal-to-noise ratio (SNR). The effective SNR may then be used by a loading controller to determine bit loading information for each tone. The bit loading information may be transmitted to the other device, which may then use this information to identify the appropriate number of bits to load in each tone when transmitting data.

Abstract: An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over the first active area and the field region and a second polysilicon finger is formed over the second active area and the field region. A first dielectric layer is formed over the first active area and the field region and a second dielectric layer is formed over the second active area and the portion of the first dielectric layer over the field region. A first electrical interconnect is formed over and dielectrically isolated from the first polysilicon finger and a second electrical interconnect is formed over and dielectrically isolated from the second active area. The second electrical interconnect is electrically coupled to the second polysilicon finger.

Abstract: A method of reflective lithography includes directing an asymmetric radiation (light) beam onto a reticle of a reflective lithography system. The asymmetry in the shape of the radiation beam may be used to compensate for a non-zero (non-normal) angle of incidence of the incident radiation. The radiation source shape may be configured to produce a substantially-symmetric output from the reticle. The shape of the radiation source may be configurable by any of a variety of suitable methods, for example by use of a configurable reflective device such as a fly's eye mirror, or by use of one or more suitable mirrors, lenses, and/or slits.

Abstract: An OFDM receiver has an autocorrelation circuit configured for generating autocorrelated power values from samples of received short preamble symbols in a received data packet, and a median filter configured for generating a median autocorrelation value from at least a prescribed minimum number of the autocorrelated signal values. A comparator is configured for detecting a symbol boundary, identifying an end of the short preamble symbols, based on the autocorrelated signal values falling below a threshold that is based on the median autocorrelation value. Hence, the threshold used to identify the symbol boundary is dynamically calculated on a per-packet basis, eliminating errors due to varying energy levels or propagation characteristics from different packet sources; moreover, the median autocorrelation value minimizes effects due to noise components, minimizing false detection errors.

Abstract: An OFDM receiver has an autocorrelation circuit configured for generating an autocorrelation result from samples of received short preamble symbols in a received data packet, where the autocorrelation circuit generates each autocorrelation result based on accumulation of the samples having been received for the short preamble symbols. Hence, by using all received samples of the short preamble symbols, the autocorrelation based on accumulated samples minimizes the effect of noise and provides a more accurate coarse frequency estimation result.

Abstract: A node includes input ports that are configured to receive packets from other nodes or from devices coupled to the node and output ports that are configured to send packets to other nodes or devices. Scheduling logic may control how packets that are received via the input ports are routed to the output ports. An input port may receive a packet that has multiple destinations or recipients. The scheduling logic may be configured to route this multi-destination packet to at least one of the output ports if at least one of the packet's recipients has an input buffer available to receive the packet.

Abstract: A chip carrier for flip chip applications, according to the present invention, provides peripheral bumps and inner bumps. The inputs and outputs related to the inner bumps are routed out on an additional wiring layer by means of vias. The proposed bond layout provides a high I/O count for a predefined chip size and a predefined carrier technology.

Abstract: An apparatus, method and system for performing a race analysis on an integrated circuit design which includes incorporating effects of on-chip transistor gate length (Lgate) and resistance variations into the race analysis and modeling on circuit performance while taking into account intra-chip transistor Lgate spatial variability.

Abstract: A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.

Abstract: Various devices for mounting circuit devices and methods of making the same are provided. In aspect, a device is provided that includes a member for holding an integrated circuit. The member contains a first plurality of carbon nanotubes to enhance the thermal conductivity thereof. At least one conductor member projects from the member. In another aspect, a method of fabricating an interface for an electronic component is provided that includes forming a member containing a first plurality of carbon nanotubes and forming at least one conductor on the member.

Abstract: A delay-locked loop (DLL) has a counter that is incremented or decremented by the loop in the process of achieving lock. The counter value is converted using an digital to analog converter (DAC) to an analog voltage that controls the delay through the delay line. During faster lock modes, the loop increments/decrements intermediate bits of the counter (with the bits less significant being held at a constant value, e.g., 0) to provide a coarse lock, rather than incrementing/decrementing the least significant bit of the counter. After coarse lock is achieved, a better lock is then achieved by incrementing/decrementing the counter using a smaller increment, i.e., a less significant bit is updated, until finally, the LSB is utilized to achieve fine lock. Utilizing the coarse lock first, and then one or more finer locks, allows the lock to be achieved more quickly.

Abstract: An integrated circuit includes at least a first and second compensation circuit that compensate for process, temperature, and other variable conditions that affect circuit performance. A compensation select circuit is coupled to selectively enable each of the first and second compensation circuits at respective first and second time periods to control a voltage on the input/output terminal to substantially equal a reference voltage and thereby determine appropriate compensation setting.