Abstract: The present invention is directed to controlling wafer temperature during rapid thermal processing. Regions and devices in an integrated circuit may be surrounded, inlayed, and overlaid with high absorptive structures to increase the average absorptivity of a region. This technique is useful for increasing average absorptivity in dense capacitive regions of integrated circuits. These dense capacitive regions typically have large areas of exposed low absorptivity polysilicon during rapid thermal processing steps. The exposed low absorptivity regions absorb less energy than other regions of the integrated circuit. As such, the RTP temperature varies between regions of the integrated circuit, causing variance in device size and characteristics. Adding absorptivity structures increase the absorption of energy in these regions, reducing temperature variance during RTP. The reduced temperature variance results in uniform manufacture of device.

Abstract: An integrated circuit comprises an ESD protection circuit including an inductor coupled between an input terminal and a ground terminal at which an RF signal is applied. The inductor is designed so as to provide a sufficient current capability required in typical ESD events. Moreover, the inductance of the inductor is selected to define, in combination with any parasitic capacitance present, a resonance tank with a resonant frequency that is matched to the RF signal. Accordingly, the operating frequency of the integrated circuit is not limited by the ESD protection circuit. In a further embodiment, an output terminal is ESD protected by an inductor that is coupled to an auxiliary voltage serving to bias an output transistor. Moreover, clamping elements, such as diodes, are provided between the auxiliary voltage and the supply voltage and between the auxiliary voltage and ground potential.

Abstract: A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.

Abstract: An extended host controller test mode support is provided. In the example of USB host controllers, an enhanced host controller is provided to control the high-speed traffic. Further at least one companion host controller controls the full-speed and/or low-speed traffic. The enhanced host controller comprises a test circuit for controlling a USB transceiver macrocell to perform full-speed and/or low-speed test functions. The test functions may include a test-J function, a test-K function, a single-ended-zero test function, and the sending of test patterns.

Abstract: A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract: A semiconductor on insulator (SOI) device is comprised of a layer of a dielectric material having a perovskite lattice, such as a rare earth scandate. The dielectric material is selected to have an effective lattice constant that enables growth of semiconductor material having a diamond lattice directly on the dielectric. Examples of the rare earth scandate dielectric include gadolinium scandate (GdScO3), dysprosium scandate (DyScO3), and alloys of gadolinium and dysprosium scandate (Gd1?xDyxScO3).

Abstract: A system may include a dispatch unit, a scheduler, and an execution core. The dispatch unit may be configured to modify a load operation to include a register-to-register move operation in response to an indication that a speculative result of the load operation is linked to a data value identified by a first tag. The scheduler may be coupled to the dispatch unit and configured to issue the register-to-register move operation in response to availability of the data value. The execution core may be configured to execute the register-to-register move operation by outputting the data value and a tag indicating that the data value is the result of the load operation.

Abstract: Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.

Abstract: Disclosed herein is a method comprised of providing a wafer comprised of a bulk substrate, an insulating layer positioned above the bulk substrate, and a semiconducting layer positioned above the insulating layer, forming an opening in the semiconducting layer and the insulating layer to thereby expose a surface area of the bulk substrate, forming an alignment mark in the bulk substrate within the exposed surface area of the bulk substrate, and forming a layer of material above the alignment mark and in the opening. A wafer is also disclosed herein that is comprised of a bulk substrate, an insulating layer positioned above the bulk substrate, a semiconducting layer positioned above the insulating layer, an opening formed in the semiconducting layer and the insulating layer, an alignment mark formed in the bulk substrate within an area defined by the opening, and a layer of material positioned above the alignment mark and within the opening.

Abstract: Packets may be routed within a node or a network device using independent input buffers for each interface and a centralized scheduler. By employing a centralized scheduler, the risks of starvation and unfairness may be reduced. Furthermore, a centralized scheduler may be able to track the relative arrival order of all of the packets received by a node or network device, and thus older packets may tend to be routed before younger packets, leading to improved performance. Also, by maintaining independent buffers for each interface, more efficient physical routing may be achieved within a node or network device.

Abstract: Access is provided to internal analog voltage signals on internal analog nodes of an integrated circuit, without distortion of the internal analog voltage signals. An integrated circuit includes a voltage access circuit having buffered multiplexer circuits in proximity to respective groups of internal analog nodes for respective internal analog voltage signals. Each voltage access circuit outputs a selected one of the corresponding group of internal analog voltage signals as a buffered analog node signal. The voltage access circuit also includes a buffering output circuit configured for outputting a selected one of the buffered analog node signals from the respective buffered multiplexer circuits, as a buffered voltage signal, to an output pad configured for supplying the buffered voltage signal to an external probe. Successively larger buffer stages minimize loading on the internal analog nodes, while providing sufficient power for outputting the buffered voltage signal to the external probe.

Abstract: The present invention is generally directed to various advanced process control methodologies for thermal oxidation processes, and various systems for accomplishing same. In one illustrative embodiment, the method comprises measuring an ambient pressure of an environment external to an oxidation chamber, determining a correction factor based upon at least the measured ambient pressure, determining at least one parameter of a thermal oxidation process to be performed in the oxidation chamber based upon the determined correction factor, and performing the thermal oxidation process comprised of the determined parameter on at least one substrate positioned in the oxidation chamber.

Abstract: Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.

Abstract: A method and system for efficiently managing power consumption in a digital processor controls the CPU clock rate based on actual CPU workload by monitoring a measure of the CPU's activity to estimate the required clock speed consumption and adjusting the clock rate up or down to meet the actual estimated speed consumption. In an exemplary embodiment, a measure of the CPU's idleness is monitored and used, along with other parameters, to compute required clock speed changes.

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract: A first vendor generates one or more files corresponding to an integrated circuit having one or more registers. A content of the files is structured for at least one of: (i) incorporation into a boot code sequence; or (ii) access by the boot code sequence during execution. The boot code sequence is configured to initialize the registers responsive to the content during execution. The first vendor transmits the files to at least one of: (i) a second vendor that develops the boot code sequence; or (ii) a manufacturer of a system that includes the integrated circuit and the boot code sequence. A computer accessible medium comprises instructions which, when executed, generate the files described above and/or comprises the files. A method may include receiving, from the first vendor, the files described above. The content of the files is incorporated into the boot code sequence.

Abstract: A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.

Abstract: A method and system for enhanced security and manageability using secure storage. The system may include a crypto-processor and a memory coupled to receive memory transactions through the crypto-processor. The memory transactions are passed to the memory by the crypto-processor. The system may include a first processor, a second processor coupled to the first processor, and a storage device operably coupled to the first processor through the second processor. The second processor is configured to control access to the storage device. The method includes transmitting a request for a memory transaction for a storage location in the storage device and receiving the request for the memory transaction at the crypto-processor. The method also includes determining if the memory transaction is authorized for the storage location, and passing the request for the memory transaction to the storage device if the memory transaction is authorized for the storage location.

Abstract: A novel method of configuring a physical layer transceiver for providing data communications via residential wiring. A transmit section of the transceiver produces a pulse signal having selected amplitude. This pulse signal received by an input circuit in a receiver section of the transceiver is used for adjusting the gain of the input circuit to a fixed optimum level. In particular, the gain of the input circuit may be adjusted in response to at least one pulse. A calibration circuit of the transceiver includes a comparator for comparing the receive signal produced at the output of the input circuit, with a threshold level, and controller that supplies the input circuit with a gain control value, and sets the threshold level. The controller reduce the gain control value to decrease the gain of the input circuit when the receive signal exceeds the threshold level. The gain control value is increased to raise the gain of the input circuit when the receive signal is less than the threshold level.