Patents Assigned to Advanced Micro Devices
  • Method for semiconductor gate line dimension reduction
    Patent number: 7268066
    Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: September 11, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas J. Bonser, Marina V. Plat, Chih Yuh Yang, Scott A. Bell, Srikanteswara Dakshina-Murthy, Philip A. Fisher, Christopher F. Lyons
  • Method and system for controlling the chemical mechanical polishing of substrates by calculating an overpolishing time and/or a polishing time of a final polishing step
    Patent number: 7268000
    Abstract: A method and a controller for the chemical mechanical polishing (CMP) of substrates and, in particular, for the chemical mechanical polishing of metallization layers is disclosed. In a linear model of the CMP process, the erosion of the metallization layer to be treated is determined by the overpolish time and possibly by an extra polish time on a separate polishing platen for polishing the dielectric layer, wherein the CMP inherent characteristics are represented by sensitivity parameters derived empirically. Moreover, the control operation is designed so that even with a certain inaccuracy of the sensitivity parameters due to subtle process variations, a reasonable controller response is obtained.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: September 11, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dirk Wollstein, Jan Raebiger, Gerd Marxsen
  • Arrangement for receiving and transmitting PCI-X data according to selected data modes
    Patent number: 7269681
    Abstract: An integrated device (e.g., an integrated PCI bridge device) buffers received PCI bus strobe signals and distributes strobe signals for PCI receive data relative to the PCI data lines, enabling all PCI receive data to be latched using locally-generated PCI strobe signals generated based on the same PCI bus strobe signals. In addition, data line latch modules having primary and secondary flip-flops enable the PCI receive data to be held for an entire clock cycle, optimizing conversion between a PCI clock domain and a local clock domain of the PCI bridge device. A transmission circuit also can be configured to transmit data according to either double data rate (DDR) mode or quad data rate (QDR) mode in an efficient manner.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: September 11, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Austen John Hypher, Richard W. Reeves, Gerald Robert Talbot
  • Decode structure with parallel rotation
    Patent number: 7268591
    Abstract: A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2n locations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address bits. The rotation logic is also coupled to receive m rotation bits indicating a number of locations the first address is to be shifted if the first address falls within a specified range of addresses. The rotation logic and the address decoder are configured to operate in parallel with each other. Address selection logic is coupled to receive a first plurality of outputs from the address decoder and a second plurality of outputs from the rotation logic and is further configured to select a second address based on the first and second pluralities of outputs.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: September 11, 2007
    Assignee: Advanced Micro Devices , Inc.
    Inventors: Jan-Michael Huber, Michael K. Ciraula
  • System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
    Patent number: 7269804
    Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: September 11, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Cyrus E. Tabery, Todd P. Lukanc, Chris Haidinyak, Luigi Capodieci, Carl P. Babcock, Hung-eil Kim, Christopher A. Spence
  • PCI-X error correcting code (ECC) pin sharing configuration
    Patent number: 7269679
    Abstract: A method is provided for utilizing four error correcting code (ECC) pin connections of a PCI/PCI-X bus for one of Grant (GNT) and Request (REQ) pin connections. The method determines a mode of the PCI bus to be PCI-X Mode 1, PCI-X Mode 2, or PCI. If the determined mode is PCI-X Mode 2, the four ECC pin connections are used as ECC pin connections, and if the determined mode is PCI or PCI-X Mode 1, each of the four ECC pin connections is used as a GNT pin connection or a REQ pin connection.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: September 11, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hanwoo Cho, Richard W. Reeves
  • SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES
    Publication number: 20070209030
    Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
    Type: Application
    Filed: April 30, 2007
    Publication date: September 6, 2007
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Cyrus Tabery, Todd Lukanc, Chris Haidinyak, Luigi Capodieci, Carl Babcock, Hung-eil Kim, Christopher Spence
  • Semiconductor substrate layer configured for inducement of compressive or expansive force
    Patent number: 7265420
    Abstract: An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: September 4, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mario M. Pelella, Simon S. Chan
  • Speculation pointers to identify data-speculative operations in microprocessor
    Patent number: 7266673
    Abstract: A microprocessor may include a retire queue and one or more data speculation verification units. The data speculation verification units are each configured to verify data speculation performed on operations. Each data speculation verification unit generates a respective speculation pointer identifying outstanding operations on which data speculation has been verified by that data speculation verification unit. The retire queue is configured to selectively retire operations dependent on the speculation pointer received from each of the data speculation verification units.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: September 4, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael A. Filippo, James K. Pickett, Benjamin T. Sander
  • Embedded channel adapter having link layer configured for concurrent retrieval of payload data during packet transmission
    Patent number: 7266614
    Abstract: An host channel adapter embedded within a processor device includes a transport layer module, a transport layer buffer, a link layer module, and a link layer buffer configured for storing at least two packets to be transmitted by the embedded host channel adapter. The transport layer module is configured for generating, for each packet to be transmitted, a transport layer header, and storing in the transport layer buffer the transport layer header and a corresponding identifier that specifies a stored location of a payload for the transport layer header. The link layer module includes payload fetch logic configured for fetching the payload based on the corresponding identifier, enabling the link layer module to construct one of the two packets to be transmitted concurrently during transmission of the second of the two packets.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: September 4, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph D. Winkles, Joseph A. Bailey, Norman M. Hack
  • Programmable pattern generation for dynamic bus signal integrity analysis
    Patent number: 7266488
    Abstract: A technique for performing signal integrity analysis of a system includes providing a stimulus pattern and a model of the system and performing analog simulation of the model utilizing the stimulus pattern. The stimulus pattern includes sequences of signal transitions with associated transition times and the sequences of signal transitions conform to a bus protocol and the associated transition times are according to characteristics of the system. The stimulus pattern is generated by initializing each of the sequences of signal transitions to an initial signal value and the associated transition times to an initial time, generating subsequent signal values and subsequent transition times by applying protocol rules and calculating timing adjustments for each of a list of transactions; the subsequent signal values and subsequent transition times to be added to the sequences of signal transitions.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: September 4, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas E. Wallace, Jr., Jonathan P. Dowling
  • Remote management mechanism to prevent illegal system commands
    Patent number: 7263716
    Abstract: An integrated circuit, a computer system, and a method for authorizing RMCP requests. The method includes receiving a request for a system action and initiating a timer. The method also includes generating an authorization request for the system action and evaluating a result of the authorization request for the system action if received before an expiration of the timer. The method also includes granting the request for the system action if the expiration of the timer occurs before the result of the authorization request for the system action is received.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dale E. Gulick
  • Selective channel implantation for forming semiconductor devices with different threshold voltages
    Patent number: 7262104
    Abstract: Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semiconductor devices.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Haihong Wang, Shibly S. Ahmed, Bin Yu
  • Method and apparatus for correlating semiconductor process data with known prior process data
    Patent number: 7263451
    Abstract: A method for correlating semiconductor process data analyzes a semiconductor device that has been treated by a process, to produce process data related to the process. The data is converted into an image pattern, and automatic image retrieval is used to identify other devices having similar images. The process data is then correlated with prior process data of the other devices having the similar images.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeffrey P. Erhardt, Shivananda S. Shetty, Paul J. Steffan
  • System and method for operating components of an integrated circuit at independent frequencies and/or voltages
    Patent number: 7263457
    Abstract: Multiple logic cores of integrated circuits and processors may be configured to operate at frequencies and voltages independently of each other. Additionally, other components, such as a common bridge configured to interface with the logic cores, may operate at a voltage and frequency independent of the voltage and frequency at which the logic cores are operating. The operating frequency and/or voltage of a logic core may be independently adjusted for various reasons, including power management and temperature control. Logic circuitry at an interface between the controller and the logic cores may translate logic signals from one voltage and/or frequency to another to enable communication between the bridge and the logic core when the two are operating at different voltages and/or frequencies.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott A. White, William A. Hughes, Philip E. Madrid
  • System and method for validating a memory file that links speculative results of load operations to register values
    Patent number: 7263600
    Abstract: A system and method for linking speculative results of load operations to register values. A system includes a memory file including an entry configured to store a first addressing pattern and a first tag. The memory file is configured to compare the first addressing pattern to a second addressing pattern of a load operation, and to link a data value identified by the first tag to a speculative result of the load operation if there is a match. The system further includes an execution core coupled to the memory file and configured to access the speculative result when executing a second operation that is dependent on the load operation, and a load store unit coupled to the memory file and configured to verify the link between the data value and the speculative result of the load operation by performing a comparison between one or more addresses.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin T. Sander, Krishnan V. Ramani, Ramsey W. Haddad, Mitchell Alsup
  • Simplified optical proximity correction based on 1-dimension versus 2-dimension pattern shape classification
    Patent number: 7263683
    Abstract: A system that facilitates optical proximity correction comprises a layout that is desirably transferred to a silicon wafer, and an optical proximity correction component that alters the layout based at least in part upon a distinction between one-dimensional patterns and two-dimensional patterns within the layout. The system can comprise a block generator that replaces two-dimensional patterns within the layout with blocks. A model-based optical proximity correction component thereafter performs model-based optical proximity correction upon one-dimensional patterns within the layout.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Luigi Capodieci
  • Method and system for converting tool process ability based upon work in progress characteristics
    Patent number: 7263408
    Abstract: The present invention is generally directed to methods and systems for converting tool processing ability based upon work in progress considerations. In one illustrative embodiment, the method includes identifying a plurality of wafers to be processed in one of a plurality of tools, identifying, on a collective basis, a number of different process operations to be performed in processing the wafers and a number of wafers to be processed in accordance with each of the different process operations, changing a processing ability of at least one of the tools based upon the number of wafers to be processed in accordance with the different process operations, and processing at least one of the wafers in at least one of the tools wherein the processing ability was changed.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Troy Anthony Tanzer, Elizabeth Weaver
  • Organic BARC with adjustable etch rate
    Patent number: 7262138
    Abstract: Systems and method for adjusting an etch rate of an organic bottom antireflective coating (BARC) layer on a wafer. The BARC layer can be exposed to an energy source at varied intensities to determine a relationship between bake temperature and solubility of the BARC after baking, which correlates to a rate at which the BARC can be etched. The BARC can be a cross-linking BARC, which becomes more cross-linked as bake temperature is increased, resulting in decreased etch rate, or can be a cleaving BARC, which is subject to removal of etch-resistant monomers as bake temperature is increased, resulting in increased etch rate. Thus, the invention provides for adjustable BARC etch rates that can be aligned to an etch rate of a photoresist deposited over the BARC to permit concurrent etching of both layers while mitigating structural defects that can occur if etch rates of the respective layers differ.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Ramkumar Subramanian, Gilles Amblard
  • Use of supercritical fluid to dry wafer and clean lens in immersion lithography
    Patent number: 7262422
    Abstract: Disclosed are immersion lithography methods and systems involving irradiating a photoresist through a lens and an immersion liquid of an immersion lithography tool, the immersion liquid in an immersion space contacting the lens and the photoresist; removing the immersion liquid from the immersion space; charging the immersion space with a supercritical fluid; removing the supercritical fluid from the immersion space; and charging the immersion space with immersion liquid.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: August 28, 2007
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Bhanwar Singh, Khoi A. Phan