Abstract: A method and an apparatus for organizing production data is provided. The method comprises performing at least one process run of semiconductor devices, and recording at least one manufacturing tag associated with the process run of semiconductor devices. The method further comprises performing metrology upon at least one process run of the semiconductor device for acquiring metrology data and for performing a metrology data stackification process upon the metrology data using the manufacturing tag for organizing and stacking the metrology data. The method further comprises modifying at least one control parameter is modified based upon the stacked metrology data.

Abstract: A phase error corrector circuit and method are disclosed. In one embodiment, a phase error corrector circuit delays a PSK modulated signal and multiplies the delayed PSK modulated signal by the PSK modulated signal in order to generate a forward phase correction signal. The input signal is then mixed with the forward phase correction signal. In another embodiment, a phase error corrector circuit calculates a forward phase offset of a complex PSK modulated signal. The complex PSK modulated signal is phase shifted in a mixer by a phase difference offset in order to generate a phase corrected signal. A backward phase correction means calculates a backward phase offset based on the phase corrected signal. A subtractor subtracts the forward phase offset from the backward phase offset for outputting a difference phase offset to the mixer.

Abstract: A command storage technique that fulfils ordering rules is provided. This technique may be used in HyperTransport compliant southbridge devices. A command transmit engine comprises a command storage unit that is adapted to receive incoming commands of different command types and store the command in the order in which the commands were received. The command transmit engine further comprises an ordering rule controller that is connected to the command storage unit to select stored commands to be transmitted. The ordering rule controller is adapted to perform the selection according to predefined command ordering rules. The command ordering rules are command type dependent.

Abstract: In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the bulk substrate being doped with a first type of dopant material and a first well formed in the bulk substrate, the first well being doped with a second type of dopant material that is of a type opposite the first type of dopant material. The device further comprises a second well formed in the bulk substrate within the first well, the second well being doped with a dopant material that is the same type as the first type of dopant material, the transistor being formed in the active layer above the second well, an electrical contact for the first well and an electrical contact for said second well.

Abstract: An error correction technique for data communication receivers such as WLAN (Wireless Local Area Network) receivers is provided. The error correction technique is for correcting a frequency and/or phase error in an incoming digitally modulated signal. A constellation manipulator is provided that is adapted to manipulate the phase constellation system of the incoming digitally modulated system by mapping each constellation point of the phase constellation system to a predefined range of phase angles. The predefined range has a width of less than 2?. Further, an error detector is provided that is connected to receive data from the constellation manipulator. The data pertains to the manipulated phase constellation system. The error detector is adapted to evaluate the data to detect the frequency and/or phase error.

Abstract: There is disclosed herein a multi-port frequency step-down queue that efficiently transfers data from a fast clock domain to a slow-clock domain having parallel hardware resources. In one embodiment, the queue includes a set of registers that are sequentially selected by an input counter that receives the fast clock. As the registers are selected, they store a data item from the input data stream. The queue also includes multiple multiplexers each having inputs that are sequentially selected by an output counter that receives the slow clock. The first multiplexer is coupled to the first N registers in the queue, the second multiplexer is coupled to the second N registers in the queue, etc. In this manner, the step-down queue generates multiple output FIFO data streams at the slower clock rate. Each of the output data streams may then be processed in parallel.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a cache to cache translation data from memory; and a control unit coupled to the cache. The control unit is configured to implement address translation and memory protection for memory requests sourced by one or more input/output (I/O) devices. The memory requests sourced by the I/O devices travel in one or more first virtual channels, and the control unit is configured to transmit memory requests sourced by the control unit in at least a second virtual channel separate from the first virtual channels.

Abstract: In an embodiment, a computer system comprises a processor; a memory management module comprising a plurality of instructions executable on the processor; a memory coupled to the processor; and an input/output memory management unit (IOMMU) coupled to the memory. The IOMMU is configured to implement address translation and memory protection for memory operations sourced by one or more input/output (I/O) devices. The memory stores a command queue during use. The memory management module is configured to write one or more control commands to the command queue, and the IOMMU is configured to read the control commands from the command queue and execute the control commands.

Abstract: In an embodiment, an input/output memory management unit (IOMMU) is configured to receive a completion wait command defined to ensure that one or more preceding invalidation commands are completed by the IOMMU prior to a completion of the completion wait command. The IOMMU is configured to respond to the completion wait command by delaying completion of the completion wait command until: (1) a read response corresponding to each outstanding memory read operation that depends on a translation entry that is invalidated by the preceding invalidation commands is received; and (2) the control unit transmits one or more operations upstream to ensure that each memory write operation that depends on the translation table entry that is invalidated by the preceding invalidation commands has at least reached a bridge to a coherent fabric in the computer system and has become visible to the system.

Abstract: Methods of fabricating halo regions are provided. In one aspect, a method is provided of fabricating a first halo region and a second halo region for a circuit device of a first conductivity type and having a gate structure with first and second sidewalls. The first halo region of a second conductivity type is formed by implanting the substrate with impurities in a first direction toward the first sidewall of the gate structure. The second halo region of the second conductivity type is formed by implanting the substrate with impurities in a second direction toward the second sidewall of the gate structure. The first and second halo regions are formed without implanting impurities in a direction substantially perpendicular to the first and second directions.

Abstract: According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

Abstract: Double data rate (DDR) synchronous dynamic random access memory (SDRAM) data is sampled into a synchronization circuit on both rising and falling edges of a data strobe (DQS) signal, into separate latches. A delay calculation and timing synchronization unit determines the location of the data strobe signal relative to rising/falling edges of an internal clock, then decides which sample to transfer into the internal data path and whether to use the rising or falling internal clock edge. Every DDR-SDRAM read transaction is thus automatically synchronized without the need for predetermined delay(s), allowing a wide range of operating frequencies and frequency variations to be accommodated.

Abstract: The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

Abstract: The present invention relates to visually monitoring an interior portion of a processing chamber in a semiconductor processing system. An image collector collects images of the interior of the chamber and provides an image signal indicative of a visual representation of the interior of the chamber. A viewing station receives the image signal and displays a visual representation of the interior of the chamber.

Abstract: A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

Abstract: The present invention relates methods for patching WWAN (Wireless Wide Area Network) communication devices and corresponding WWAN communication devices, integrated circuit chips and computer-readable media. The WWAN communication device includes a first processor, a second processor and a memory. The first processor is arranged to process patches updating software running on the WWAN communication device. The second processor is arranged to provide a first set of the patches to the first processor. The memory stores a second set of the patches to be processed by the first processor. The second processor is further arranged to send a patch end signal to the first processor, the patch end signal causing the first processor to stop processing of patches provided by the second processor. The first processor is further arranged to process the patches stored in the memory independently of the patch end signal.

Abstract: A method and apparatus of the present invention provides a verified computing environment for a personal Internet communicator. In various embodiments of the invention, the functionality of software files on a personal Internet communicator can be modified based on the Pay-State of the user. Upon a request to load a particular software package, the verification module uses a verification file list containing approved software packages and also uses the pay status of the user to determine which software packages can be executed. The personal Internet communicator is operable to provide limited functionality of certain software packages based on a first pay state and to offer no functionality based on a second pay state, such as the situation where a user has discontinued the use of internet service.

Abstract: The present invention provides a method and apparatus to restore the operating system of a personal internet communicator (PIC) to a “known good” operational state in the event of a catastrophic failure. In an embodiment of the invention, the hard drive of the personal internet communicator is organized in three partitions: 1) a partition for the operating system and related files; 2) a user data partition; and 3) a “restore” partition. The restore partition is hidden by modifying the type of partition that can be detected by the user or any operating system. Upon a catastrophic failure, the system can be returned to an operational state by performing a sector-by-sector restoration to copy an image of the operating system and related system files back to the operating system partition. In various embodiments of the invention, the PIC system state is continuously monitored by a “registry sniffing” routine that maintains a file containing data corresponding to the system state of the PIC.

Abstract: According to the present invention, a metal and a barrier material, such as copper and a tantalum-based barrier material, are effectively removed from the wafer edge and especially from the bevel by using an etchant that comprises a diluted mixture of hydrofluoric acid and nitric acid. The method is compatible with currently available etch modules for removing metal from the wafer edge, wherein, depending on the hardware specifics, copper, barrier material and dielectric material may be removed in a single etch step, or a first etch step may be performed substantially without any nitric acid so as to avoid the formation of nitric oxides. In this way, the formation of instable layer stacks may be substantially avoided, thereby reducing the risk of material delamination from the substrate edge.

Abstract: A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.