Patents Assigned to Advanced Semiconductor Engineering
  • Publication number: 20180129062
    Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.
    Type: Application
    Filed: November 9, 2016
    Publication date: May 10, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Feng CHIANG, Tsung-Tang TSAI, Min Lung HUANG
  • Publication number: 20180128612
    Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.
    Type: Application
    Filed: January 4, 2018
    Publication date: May 10, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Seungbae Park, Yu-Ho Hsu, Chin-Li Kao, Tai-Yuan Huang
  • Publication number: 20180122750
    Abstract: Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip, and the supporter includes a recessed portion. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.
    Type: Application
    Filed: October 24, 2017
    Publication date: May 3, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Patent number: 9960121
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 1, 2018
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Publication number: 20180108602
    Abstract: A surface mount structure comprises a redistribution structure, an electrical connection and an encapsulant. The redistribution structure has a first surface and a second surface opposite the first surface. The electrical connection is on the first surface of the redistribution structure. The encapsulant encapsulates the first surface of the redistribution structure and the electrical connection. A portion of the electrical connection is exposed by the encapsulant.
    Type: Application
    Filed: July 20, 2017
    Publication date: April 19, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung-Liang YEH, Meng-Jen WANG, Tsung-Yueh TSAI, Chih-Ming HUNG
  • Publication number: 20180090466
    Abstract: A semiconductor device package includes a substrate, electronic components disposed over a surface of the substrate, an encapsulant encapsulating the electronic components, and a conductive compartment structure. The conductive compartment structure separates at least one first electronic component from at least one second electronic component. The conductive compartment structure includes a first portion and a second portion, the second portion includes a first end connected to the first portion and a second end exposed from a lateral surface of the encapsulant, and a width of the second portion is less than a width of the first portion.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Chi HUNG
  • Publication number: 20180083341
    Abstract: A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Han-Chee YEN
  • Publication number: 20180076177
    Abstract: A method for manufacturing a semiconductor package structure includes: (a) disposing at least one semiconductor element on a conductive structure, wherein the conductive structure includes at least one insulation layer and at least one circuit layer; (b) disposing an encapsulant on the conductive structure to cover the semiconductor element; (c) attaching a supporting structure on the conductive structure to surround the semiconductor element; and (d) disposing an upper element on the encapsulant, wherein a coefficient of thermal expansion of the upper element is in a range of variation less than or equal to about ±20% of a coefficient of thermal expansion of the circuit layer, and a bending modulus of the upper element is in a range of variation less than or equal to about ±35% of a bending modulus of the circuit layer.
    Type: Application
    Filed: November 16, 2017
    Publication date: March 15, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20180076118
    Abstract: A semiconductor device package includes a copper lead frame, a copper oxide compound layer and an encapsulant. The copper oxide compound layer is in contact with a surface of the copper lead frame. The copper oxide compound layer includes a copper(II) oxide, and a thickness of the copper oxide compound layer is in a range from about 50 nanometers to about 100 nanometers. The encapsulant is in contact with a surface of the copper oxide compound layer.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 15, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Fong SHU, Yi-Hsiu TSENG
  • Publication number: 20180076122
    Abstract: A semiconductor process includes: (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space; and (c) forming a redistribution layer on the metal layer, wherein the redistribution layer is electrically connected to the at least one metal via.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Min Lung HUANG
  • Publication number: 20180072563
    Abstract: A semiconductor device package includes: (1) a carrier; (2) a sensor element disposed on or within the carrier; and (3) a cover including a top surface, a bottom surface and an inner sidewall, the inner sidewall defining a penetrating hole extending from the top surface to the bottom surface, and the penetrating hole exposing the sensor element. The semiconductor device package is characterized such that (i) the inner sidewall is divided into an upper portion and a lower portion, the upper portion is substantially perpendicular to the top surface, and the lower portion is tilted; or (ii) the entire inner sidewall is tilted. The lower portion of the inner sidewall or the entire inner sidewall is tilted at an angle of between about 10° to less than about 90°, relative to the top surface.
    Type: Application
    Filed: November 16, 2017
    Publication date: March 15, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ching-Han HUANG, Hsun-Wei CHAN, Yu-Hsuan TSAI
  • Publication number: 20180068962
    Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).
    Type: Application
    Filed: July 13, 2017
    Publication date: March 8, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung CHEN, Yu-Hsuan TSAI, Yu-Ying LEE, Sheng-Ming WANG, Wun-Jheng SYU
  • Publication number: 20180066982
    Abstract: The present disclosure relates to an optical device. The optical device comprises an electronic component, a plurality of light conducting pillars and an opaque layer. The electronic component includes a plurality of pixels. Each of the light conducting pillars is disposed over a corresponding pixel of the plurality of pixels of the electronic component. The opaque layer covers a lateral surface of each of the light conducting pillars.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 8, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Min PENG, Ching-Han HUANG, Lu-Ming LAI
  • Publication number: 20180061805
    Abstract: A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.
    Type: Application
    Filed: August 22, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Publication number: 20180061815
    Abstract: A semiconductor package device comprises a circuit layer, an electronic component disposed on the circuit layer, a package element and a first encapsulant. The package element is disposed on the circuit layer. The package element includes at least two electrical contacts electrically connected to the circuit layer. The first encapsulant is disposed on the circuit layer. The first encapsulant encapsulates the electronic component and the package element and exposes the electrical contacts of the package element.
    Type: Application
    Filed: August 17, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Publication number: 20180061767
    Abstract: A semiconductor package structure includes a semiconductor substrate, at least one semiconductor die, an encapsulant, a protection layer, a plurality of conductive elements and a redistribution layer. The semiconductor die is disposed on the semiconductor substrate. The encapsulant covers at least a portion of the semiconductor die, and has a first surface and a lateral surface. The protection layer covers the first surface and the lateral surface of the encapsulant. The conductive elements surround the lateral surface of the encapsulant. The redistribution layer electrically connects the semiconductor die and the conductive elements.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Feng CHIANG, Cong-Wei CHEN, I-Ting CHI, Shao-An CHEN
  • Publication number: 20180061813
    Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.
    Type: Application
    Filed: August 11, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Li-Hao LYU
  • Publication number: 20180061727
    Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.
    Type: Application
    Filed: August 11, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
  • Publication number: 20180061776
    Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.
    Type: Application
    Filed: August 22, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Peng YANG, Yuan-Feng CHIANG, Po-Wei LU
  • Publication number: 20180053705
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate, an electrical component disposed on the first substrate, a second substrate disposed over the electrical component, an adhesive layer, a spacer, and an encapsulation layer. The adhesive layer is disposed between the electrical component and the second substrate. The spacer directly contacts both the adhesive layer and the second substrate. The encapsulation layer is disposed between the first substrate and the second substrate.
    Type: Application
    Filed: July 19, 2017
    Publication date: February 22, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Jen WANG