Patents Assigned to Advanced Semiconductor Engineering
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Publication number: 20190035714Abstract: A semiconductor package device includes a leadframe, a first die and a package body. The leadframe includes a first die paddle and a lead. The first die paddle has a first surface and a second surface opposite to the first surface. The first die is disposed on the first surface of the first die paddle. The package body covers the first die and at least a portion of the first surface of the first die paddle and exposing the lead. The package body has a first surface and a second surface opposite to the first surface. The second surface of the package body is substantially coplanar with the second surface of the first die paddle. The lead extends from the second surface of the package body toward the first surface of the package body. A length of the lead is greater than a thickness of the package body.Type: ApplicationFiled: July 28, 2017Publication date: January 31, 2019Applicant: Advanced Semiconductor Engineering Korea, Inc.Inventors: Junyoung YANG, Sangbae PARK
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Publication number: 20190027441Abstract: An interposer comprises a first conductive wire having a first terminal and a second terminal, a first oxide layer, and an encapsulant. The first oxide layer covers the first conductive wire and exposes the first terminal and the second terminal of the first conductive wire. The encapsulant covers the first oxide layer and exposes the first terminal and the second terminal of the first conductive wire.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kun-Ming CHEN, Yuan-Feng CHIANG
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Publication number: 20190013284Abstract: A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer.Type: ApplicationFiled: July 5, 2017Publication date: January 10, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jen-Kuang FANG, Wen-Long LU
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Publication number: 20190013346Abstract: An image sensor comprises a chip, a first redistribution layer (RDL), a second RDL and a third RDL. The chip has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first RDL is disposed on the first surface of the chip and extends along the first surface of the chip and beyond the lateral surface of the chip. The second RDL is disposed on the second surface of the chip. The third RDL is disposed on the lateral surface of the chip and connects the first RDL to the second RDL.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Chi Sheng TSENG
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Publication number: 20190013289Abstract: A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.Type: ApplicationFiled: July 10, 2017Publication date: January 10, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jen-Kuang FANG, Wen-Long LU
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Patent number: 10177283Abstract: An LED package with trenches traversing a die pad to provide a mechanical interlock mechanism to strengthen bonding between the die pad and an insulator such that de-lamination is less likely to occur between the die pad and the insulator. A chip carrying region is defined by a barrier portion formed by the insulator in the trenches and in gaps between electrodes and the die pad, such that a light converting layer is confined within the barrier portion.Type: GrantFiled: April 20, 2017Date of Patent: January 8, 2019Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Hsun-Wei Chan
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Publication number: 20190006308Abstract: A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Bernd Karl APPELT
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Publication number: 20180374805Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.Type: ApplicationFiled: September 4, 2018Publication date: December 27, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang-Lin YEH, Jen-Chieh KAO, Chih-Yi HUANG, Fu-Chen CHU
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Publication number: 20180366402Abstract: The present disclosure relates to a wiring structure and a semiconductor package. The wiring structure comprises a first wiring pattern, a dielectric layer and a dummy structure. The first wiring pattern includes a conductive land having a width W1 and a surface area A, and a conductive trace having a width W2 and electrically connected to the conductive land, wherein ((W1*W2)/A)*100% about 25%. The dielectric layer covers the first wiring pattern, and the dummy structure is adjacent to the conductive trace.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wen Hung HUANG, Yan Wen CHUNG, Wei Chu SUN
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Publication number: 20180358290Abstract: A semiconductor device package includes a substrate, a first insulation layer, a support film and an interconnection structure. The substrate has a first sidewall, a first surface and a second surface opposite to the first surface. The first insulation layer is on the first surface of the substrate and has a second sidewall. The first insulation layer has a first surface and a second surface adjacent to the substrate and opposite to the first surface of the first insulation layer. The support film is on the second surface of the substrate and has a third sidewall. The support film has a first surface adjacent to the substrate and a second surface opposite to the first surface of the support film. The interconnection structure extends from the first surface of the first insulation layer to the second surface of the support film via the first insulation layer and the support film. The interconnection structure covers the first, second and third sidewalls.Type: ApplicationFiled: June 8, 2017Publication date: December 13, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Hua CHEN, Ming-Hung CHEN, Hsu-Chiang SHIH
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Publication number: 20180358291Abstract: A method for manufacturing a semiconductor device package includes providing a substrate having a first surface and a second surface opposite to the first surface; disposing a passive component layer on the first surface of the substrate; after disposing the passive component layer, forming at least one via in the substrate, wherein the via penetrates the substrate and the passive component layer; and disposing a conductive layer on the passive component layer and filling the via with the conductive layer.Type: ApplicationFiled: June 8, 2017Publication date: December 13, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Hua CHEN, Sheng-Chi HSIEH, Cheng-Yuan KUNG
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Publication number: 20180359853Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.Type: ApplicationFiled: June 13, 2017Publication date: December 13, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ming-Ze LIN, Chia Ching CHEN, Yi Chuan DING
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Publication number: 20180358276Abstract: A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Tsung CHIU, Meng-Jen WANG, Cheng-Hsi CHUANG, Hui-Ying HSIEH, Hui Hua LEE
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Publication number: 20180358501Abstract: A semiconductor package device comprises a substrate, a light emitter, a light detector and a transparent conductive film. The substrate as a first surface and a second surface opposite to the first surface. The light emitter is disposed on the first surface of the substrate and has a light emission area adjacent to the first surface of the substrate. The light detector is disposed on the first surface of the substrate and has a light receiving area adjacent to the first surface of the substrate. The transparent conducting film is disposed on the second surface of the substrate.Type: ApplicationFiled: June 9, 2017Publication date: December 13, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Ling HUANG, Ying-Chung CHEN
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Publication number: 20180350753Abstract: A semiconductor package device includes: (1) a substrate having a top surface; (2) a passive component disposed on the substrate and having a top surface; (3) an active component disposed on the substrate and having a top surface; and (4) a package body disposed on the substrate, the package body including a first portion covering the active component and the passive component, and a second portion covering the passive component, wherein a top surface of the second portion of the package body is higher than a top surface of the first portion of the package body, and the first portion and the second portion of the package body include different materials.Type: ApplicationFiled: August 8, 2018Publication date: December 6, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Hsuan LEE, Jaw-Ming Ding, Wei-Yu CHEN
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Publication number: 20180350724Abstract: A semiconductor package includes: a substrate including a conductive pad; a semiconductor device including a conductive member; and a connection element between the conductive pad and the conductive member, wherein the connection element has a sidewall, and an angle of the sidewall relative to the conductive pad is equal to or less than about 90 degrees.Type: ApplicationFiled: May 30, 2017Publication date: December 6, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Chao Cheng LIU
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Publication number: 20180350626Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.Type: ApplicationFiled: August 13, 2018Publication date: December 6, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, Yu-Ying LEE, Yu-Tzu PENG
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Publication number: 20180348454Abstract: A waveguide includes a first layer and a second layer. The first layer comprises a material of a first refractive index. The second layer is surrounded by the first layer and comprises a material of a second refractive index greater than the first refractive index. The second layer comprises a main body, a first fork and a second fork. The main body has a first substantially constant thickness. The first fork is extended from the main body and has a first tapering end exposed by the first layer. The first fork has the first substantially constant thickness. The second fork is extended from the main body and has a second tapering end exposed by the first layer. The second fork has the first substantially constant thickness.Type: ApplicationFiled: June 6, 2017Publication date: December 6, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Mei-Ju LU, Tai-Hsuan TU, Yi-Min CHIN, Wei Lun WANG, Jia-Hao ZHANG
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Publication number: 20180342471Abstract: An antenna semiconductor package device includes a first conductive layer, a second conductive layer, a first conductive element and a first directing element. The second conductive layer is over the first conductive layer and separated from the first conductive layer. The first conductive element connects the first conductive layer to the second conductive layer. The first directing element is adjacent to the first conductive layer and separated from the first conductive layer by a first gap. The first conductive element, the first conductive layer and the second conductive layer define a waveguide cavity and a radiation opening.Type: ApplicationFiled: May 24, 2017Publication date: November 29, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shao-En HSU, Huei-Shyong CHO, Shih-Wen LU
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Publication number: 20180342473Abstract: A via structure includes a base material, a first dielectric layer and a second dielectric layer. The base material includes a first surface and a second surface opposite to the first surface, and defines at least one through hole. The first dielectric layer is disposed on the first surface of the base material and includes a gradient surface exposed in the through hole of the base material. The second dielectric layer is disposed on the gradient surface of first dielectric layer.Type: ApplicationFiled: May 25, 2017Publication date: November 29, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wen-Long LU, Yuan-Feng CHIANG, Tsung-Tang TSAI