Abstract: A substrate for packaging a semiconductor device includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer. The first patterned conductive layer includes a first portion and a second portion. Each of the first portion and the second portion is embedded in the first dielectric layer and protrudes relative to the first surface of the first dielectric layer toward a direction away from the second surface of the first dielectric layer. A thickness of the first portion of the first patterned conductive layer is greater than a thickness of the second portion of the first patterned conductive layer.

Abstract: A substrate including a dielectric layer and a patterned conductive layer adjacent to the dielectric layer is provided. The patterned conductive layer comprises a first conductive pad, the first conductive pad comprises a first portion having a first concave sidewall. The substrate further includes a protection layer disposed on the patterned conductive layer, and the protection layer covers the first portion of the first conductive pad.

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate, an electrical component disposed on the first substrate, a second substrate disposed over the electrical component, an adhesive layer, a spacer, and an encapsulation layer. The adhesive layer is disposed between the electrical component and the second substrate. The spacer directly contacts both the adhesive layer and the second substrate. The encapsulation layer is disposed between the first substrate and the second substrate.

Abstract: A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.

Abstract: A substrate for packaging a semiconductor device is disclosed. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer. The first dielectric layer includes a first portion adjacent to the first surface, a second portion adjacent to the second surface, and a reinforcement structure between the first portion and the second portion. A thickness of the first portion of the first dielectric layer is different from a thickness of the second portion of the first dielectric layer.

Abstract: A semiconductor package structure includes a substrate, at least one first semiconductor element, a heat dissipation structure and an insulation layer. The at least one first semiconductor element is attached to the substrate, and has a first surface and a second surface opposite to the first surface. The first surface of the at least one first semiconductor element faces the substrate. The heat dissipation structure is disposed on the second surface of the at least one first semiconductor element. The insulation layer is disposed on the heat dissipation structure, and defines a plurality of openings extending through the insulation layer and exposing a plurality of exposed portions of the heat dissipation structure.

Abstract: A semiconductor package device comprises a first dielectric layer, a first conductive pad and a first conductive element. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first dielectric layer defines a first opening tapered from the first surface toward the second surface. The first conductive pad is within the first opening and adjacent to the second surface of the first dielectric layer. At least a portion of the first conductive element is within the first opening. The first conductive element is engaged with (e.g., abuts) a sidewall of the first opening, the first conductive element having a first surface facing toward the first conductive pad, wherein the first surface of the first conductive element is spaced apart from the first conductive pad.

Abstract: An electronic component includes a die, a first protective layer, a second protective layer, a first conductive pillar and a second conductive pillar. The die includes a conductive pad. The first protective layer is disposed on the die. The first protective layer defines a first opening to expose the conductive pad of the die. The second protective layer is disposed on the first protective layer. The second protective layer defines a second opening and a first recess. The second opening exposes the conductive pad of the die. The first conductive pillar is disposed within the second opening and electrically connected to the conductive pad. The second conductive pillar is disposed within the first recess. A height of the first conductive pillar is substantially equal to a height of the second conductive pillar. A bottom surface of the first recess is disposed between a top surface of the first protective layer and a top surface of the second protective layer.

Abstract: An integrated passive component comprises a capacitor, a first passivation layer, an inductor, an insulation layer and an external contact. The first passivation layer surrounds the capacitor. The inductor is on the first passivation layer and electrically connected to the capacitor. The inductor comprises a plurality of conductive pillars. The insulation layer is on the first passivation layer and surrounds each of the conductive pillars. The insulation layer comprises a first surface adjacent to the first passivation layer, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface. A ratio of a width of each of the conductive pillars to a height of each of the conductive pillars is about 1:7. The external contact is electrically connected to the inductor and contacts the second surface of the insulation layer and the side surface of the insulation layer.

Abstract: A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.

Abstract: A method for manufacturing a semiconductor package includes: (a) providing a package device, the package device comprising a substrate, a package body and a plurality of connecting elements, the substrate having a first surface, the package body being disposed adjacent to the first surface of the substrate, and the connecting elements being disposed adjacent to the first surface of the substrate and encapsulated by the package body; and (b) removing a portion of the package body along one or more machining paths to expose the connecting elements, wherein each machining path has one or more first paths passing over, between, or along a side of at least two connecting elements, wherein a portion of each of the at least two connecting elements is within the package body, and another portion of each of the at least two connecting elements protrudes from a surface of the package body.

Abstract: A semiconductor package device comprises a substrate, a die, an encapsulant and an antenna layer. The substrate has a top surface and a bottom surface opposite to the top surface. The die is disposed on the top surface of the substrate. The encapsulant is disposed on the top surface of the substrate and surrounds the die. The encapsulant has a top surface and defines a recess on the top surface of the encapsulant. The antenna layer is disposed on the top surface of the encapsulant and extends within the recess on the top surface of the encapsulant.

Abstract: An electrical device comprises a substrate, a first dielectric layer, a first die, an adjustable inductor and a second die. The substrate has a first surface. The first dielectric layer is disposed on the first surface of the substrate and has a first surface. The first die is surrounded by the first dielectric layer. The adjustable inductor is electrically connected to the first die. The adjustable inductor comprises a plurality of pillars surrounded by the first dielectric layer, a plurality of first metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars, and a plurality of second metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars. A width of at least one of the second metal strips is different than a width of at least one of the first metal strips. The second die is electrically connected to the adjustable inductor.

Abstract: A Micro Electro-Mechanical System (MEMS) device package includes a first circuit layer, a partition wall, a MEMS component, a second circuit layer and a polymeric dielectric layer. The partition wall is disposed over the first circuit layer. The MEMS component is disposed over the partition wall and electrically connected to the first circuit layer. The first circuit layer, the partition wall and the MEMS component enclose a space. The second circuit layer is disposed over and electrically connected to the first circuit layer. The polymeric dielectric layer is disposed between the first circuit layer and the second circuit layer.

Abstract: A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.

Abstract: A semiconductor package device comprises a passivation layer, a conductive element, a redistribution layer (RDL) and an electronic component. The passivation layer has a first surface and second surface opposite to the first surface. The conductive element is within the passivation layer. The conductive element defines a recess facing the second surface of the passivation layer. The RDL is on the passivation layer and electrically connected with the conductive element. The electronic component is disposed on the RDL and electrically connected with the RDL.

Abstract: In one or more embodiments, an apparatus for processing a wafer includes a ceramic wall, a metal wall and a frame. The ceramic wall defines a chamber for accommodating the wafer. The ceramic wall has a first surface defining a first opening. The metal wall surrounds the ceramic wall. The metal wall has a second surface defining a second opening adjacent to the first opening. The frame covers the second surface.

Abstract: A semiconductor package device comprises a substrate, an electrical component and a package body. The electrical component is disposed on the substrate. The electrical component has an active surface facing toward the substrate and a back surface opposite to the active surface. The back surface has a first portion and a second portion surrounding the first portion. The first portion of the back surface of the electrical component includes a plurality of pillars. The package body is disposed on the substrate. The package body encapsulates the electrical component and exposes the back surface of the electrical component.

Abstract: The present disclosure relates to an electronic device. The electronic device comprises a substrate, a micro-electromechanical systems (MEMS) device and an attachment element. The substrate defines an opening penetrating the substrate. The MEMS device has an active surface facing away from the substrate and a sensing region facing toward the opening. The attachment element is disposed on the substrate and surrounding the opening and the sensing region of the MEMS device.

Abstract: A substrate structure includes a dielectric layer, a first circuit layer, at least one conductive structure and a first protective layer. The first circuit layer is disposed adjacent to a first surface of the dielectric layer. The conductive structure includes a first portion and a second portion. The first portion is disposed on the first circuit layer. The first protective layer is disposed on the dielectric layer and contacts at least a portion of a sidewall of the first portion of the conductive structure. The first circuit layer and the conductive structure are integrally formed.