Abstract: A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining information concerning a test class using a graphical user interface. Further, it comprises generating a first header file automatically, wherein the first header file comprises the information concerning the test class. Next, it comprises importing the first header file into a test plan operable to execute using a tester operating system wherein the test plan comprises instances of the test class. It further comprises, generating a second header file from the first header file automatically, wherein the second header file is a header file for the test class. The method also comprises validating the test plan using the tester operating system. Finally, the method comprises loading the test plan and a compiled module onto the tester operating system for execution, wherein the compiled module is a compiled translation of the test class.

Abstract: A method for debugging test procedures for automated device testing is disclosed. The method comprises receiving a command to update at least one modified test procedure modified during a first debugging session and saving state information for a test plan, wherein the state information comprises information regarding a breakpoint entry location, and wherein the modified test procedure is invoked within the test plan. The method subsequently comprises suspending execution of the test plan and unloading the modified test procedure. It also comprises compiling the modified test procedure to produce a compiled file and then reloading the test procedure into the test plan using the compiled file. Finally, it comprises resuming execution of the modified test procedure in a second debugging session and breaking the execution during the second debugging session at a breakpoint corresponding to the breakpoint entry location.

Abstract: A pulse wave sensor unit includes a pressure sensor, and an adhesive tape to attach the pressure sensor to a measurement portion to be measured. The pressure sensor includes a diaphragm part, and an annular support part which supports the diaphragm part and has an aperture for allowing the diaphragm part to face the measurement portion, and a closed space is able to be formed between the diaphragm part and the measurement portion by attaching the pressure sensor to the measurement portion using the adhesive tape.

Abstract: There is provided an electronic component handling apparatus which can be reduced in size or can improve the throughput when the number of contact arms is increased. A handler comprises: a plurality of contact arms which are arrayed along a first direction, each of the plurality of contact arms including a holding part which holds a DUT and including an adjustment unit which moves the holding part relative to a base part of each contact arm; an imaging unit capable of imaging the DUT and the holding part; an operation unit which operates the adjustment unit; and a moving unit which moves the imaging unit and the operation unit along an X direction. The adjustment unit adjusts the relative position of the holding part according to an operation of the operation unit.

Abstract: Embodiments of the present invention provide an RF probe for coupling out a probe signal from a transmission line of a circuit. The RF probe includes at least two probe pins having first ends for contacting the circuit and second ends. Furthermore, the RF probe includes a provider for providing a variable impedance at the second ends of the probe pins. The RF probe is configured to provide the probe signal based on a signal propagating along at least one of the probe pins.

Abstract: Provided is a handler apparatus that conveys a device under test to a test socket, including: an actuator that, prior to fitting of a device holder to the test socket, fits the device holder, and adjusts a position of the device under test on the device holder; and a conveyer that conveys the device holder in which a position of the device under test has been adjusted, to fit the test socket, where the device holder includes: an inner unit to mount the device under test; an outer unit to retain the inner unit to be movable; and a release button to release a lock of movement of the inner unit, in response to being pressed from a side to which the device under test is mounted, and the actuator sets the inner unit to be movable by pressing the release button and adjusts a position of the inner unit.

Abstract: A wireless power transmitting apparatus transmits an electric power signal comprising any one from among an electric field, a magnetic field, and an electromagnetic field to a wireless power receiving apparatus. A transmission antenna includes a transmission coil. An automatic tuning assist circuit is coupled in series with the transmission antenna. A power supply applies an AC driving voltage across both terminals of a series circuit that comprises the transmission antenna and the automatic tuning assist circuit. A first controller switches on and off multiple switches in synchronization with the driving voltage. A voltage monitoring unit monitors the voltage that develops at an auxiliary capacitor.

Abstract: A switchable signal routing circuit for routing a signal between at least one input port and at least one output port is provided. The ports are connected via variable resistors to a common node, wherein the switchable signal routing circuit is configured to set resistance values of the variable resistors in dependence on a number of active ports.

Abstract: A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values.

Abstract: A test carrier includes a base member that holds a die and a cover member. The base member includes a board having a wiring line that is electrically connected to the die. The wiring line includes a wiring line and a resistive portion having a resistance value that is higher than the resistance value of the wiring line.

Abstract: A computer implemented process is described for testing multiple electronic devices under test (DUTs). A design test pattern or command/instruction is generated with an electronic design automation tool (EDA). The generated design test pattern and command/instruction is sent directly to an automated test equipment apparatus (ATE) over a UNIX or scripting language based, and/or a network based, communication pipeline. The ATE converts the sent design test pattern to an instance of the test pattern directly executable by the ATE. The ATE apparatus inputs test signals to each of the multiple electronic DUTs based on the executable test pattern. The ATE apparatus then receives, from each of the multiple electronic DUTs, a test result based on the input test signals. The ATE returns the received test result, and a report of an action responsive to the command/instruction to the EDA tool, which may then process the test results and report.

Abstract: An exposure apparatus is configured to include an electronic optical system 108 that generates an electron ray and irradiates a wafer W with the electron ray, a wafer stage WS that holds the wafer W, and an electron detector 44 and a fog preventing mechanism 70 that are placed between the electronic optical system 108 and the wafer stage WS. A substrate 71 constitutes the fog preventing mechanism 70, and opening holes 71a0 that penetrate up to the upper surface of the substrate 71 are formed in a first area of the bottom surface of the substrate 71, and opening holes 71a0 that are closed in the substrate 71 are formed in a second area of the bottom surface.

Abstract: To test a probe card with an examination apparatus that tests a device under test, provided is a test system that tests a device under test and includes a test section that includes a plurality of test units that input or output a signal; a probe card that includes a plurality of probe terminals connected to a terminal of the device under test, and transmits signals between the device under test and the test section; and a wafer for testing that is connected to the probe card, instead of the device under test, when testing the probe card, and includes a connection wire that electrically connects two of the probe terminals to each other. The test section measures output of at least one of two test units connected to the two probe terminals, and judges pass/fail of the two probe terminals.

Abstract: In an embodiment, a testing system includes a frame, a DUT (device under test) testing module. The frame has at least one aperture extending from a front side of the frame to a rear side of the frame. The DUT testing module is inserted into the at least one aperture. The DUT testing module is operable to receive and hold a DUT receptacle including an electrical interface, an air flow interface, and a DUT coupled to the electrical interface. The DUT receptacle is configured to enclose and hold inside the DUT. Further, the DUT testing module is operable to couple to and to use the electrical interface and the air flow interface to perform a test at a controlled temperature on the DUT that is inside of the DUT receptacle.

Abstract: The method for forming a semiconductor probe tip comprises depositing a first copper layer onto exposed electrically conductive areas of a wafer. The first copper layer surrounds a non-conductive polymer structure on the wafer. The non-conductive polymer structure is removed to form a primary cavity in the first copper layer. The wafer and the primary cavity are coated with a polymer layer. Regions of the polymer layer are removed to form a secondary cavity within and alongside the primary cavity. A metal layer is deposited on exposed electrically conductive areas of the wafer and within bounds of the secondary cavity.

Abstract: A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination.

Abstract: A handler apparatus adjusts a position of an actuator and enhances positional accuracy of a device under test. Provided is a handler apparatus that conveys a device under test to a test socket, including: an actuator that, prior to fitting of a device holder holding the device under test to the test socket, fits the device holder, and adjusts a position of the device under test on the device holder; and an actuator adjusting section that adjusts an amount of driving of the actuator by causing the actuator to fit an actuator fitting unit.

Abstract: A preferred method for efficiently tuning RF ports while avoiding conventional labor intensive, step-by-step processes is disclosed. The method may use at least three tuning blocks (comprised of capacitors and inductors) in a series topology and at least three tuning blocks in a shunt topology. These tuning blocks will yield two circles that can be charted on the Smith chart. Those circles may then be centered along the centerline of the Smith chart to adjust for latency, and then expanded to adjust for the losses. Once those circles have been expanded, the circle (either series or shunt) that encompasses one the Smith chart reference circles is used and the traditional Smith chart methodology can be used to tune the RF port.