Abstract: A clock generator is provided for a transmitter in a transceiver adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit recovers a receive clock signal and outputs a reference clock signal. The clock generator includes a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock outputs a local clock signal. The frequency difference detector outputs a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer outputs a transmit clock signal having a same frequency as the recovered receive clock signal.

Abstract: Methods and apparatus for synchronizing a first clock of a transmit node and a second clock of receive node in a packet network are provided. Consecutive intervals of time-stamped packets transferred from the transmit node to the receive node are selected. The consecutive intervals have a difference in delay noise within a defined acceptance window. A correction factor is determined for the second clock in accordance with transmit and receive time stamps of transferred time-stamped packets bounding the consecutive intervals. The correction factor is applied to the second clock to synchronize the second clock of the receive node with the first clock of the transmit node.

Abstract: A circuit for, and method of, detecting a signal level on a node and a mobile telephone device incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a switch coupled between a voltage source and the node, (2) a pulse generator coupled to the switch and configured to generate a pulse to control the switch and (3) a detection circuit coupled to the node and configured to detect a signal level at the node on closure of the switch.

Abstract: A processor comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is operative to retrieve from the memory circuitry an interrupt polling instruction which causes selection of an active enabled interrupt and generation of an interrupt vector for the selected active enabled interrupt. In conjunction with the selection and generation operations, an execution context of a program thread is stored in the memory circuitry, the stored execution context being utilizable to resume the program thread at an appropriate time subsequent to interruption of that thread.

Abstract: In one embodiment, an electrical system having an LED array, a first current source connected to provide a first current to the LED array, a current-sense resistor connected to the LED array, a second current source connected to provide a second current to the current-sense resistor, a control processor, and a voltage sensor adapted to provide a corresponding sensor signal to the control processor, wherein the control processor is adapted to control the first and second current sources based on the sensor signal. The first current source having a diode with first and second sides, an inductor connected between a first reference voltage source and a first side of a diode, a capacitor connected between a second side of the diode and a second reference voltage, and a transistor connected between the first side of the diode and the second reference voltage.

Abstract: A scheduler having improved fairness is disclosed, for scheduling packets or other data blocks for transmission from a plurality of transmission elements in timeslots in a communication system. The scheduler determines credit measures for respective ones of the transmission elements, with each of said credit measures being a function of a reserved portion of an available bandwidth and a scheduled portion of said available bandwidth for a corresponding one of the transmission elements. The scheduler selects one or more of the transmission elements for scheduling in a given one of the timeslots based on the credit measures. The scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of the communication system.

Abstract: A buffer circuit for use in a node in a network-based data transport system is configurable for providing channel status information of all channels associated with a given signal in the network-based data transport system. The buffer circuit includes a memory and a controller coupled to the memory. The controller is operative: (i) to receive channel status information from a plurality of different channel status sources; (ii) to select one of the channel status sources for supplying the channel status information at a given point in time; and (iii) to store the channel status information corresponding to the selected channel status source in the memory.

Abstract: A network-based data distribution system includes a physical layer device connectable to a network processor operative in a link layer or higher layer. The physical layer device is configurable for interfacing with a plurality of destination devices via corresponding physical layer links. The physical layer device is operative to receive data traffic from the network processor and to replicate at least a portion of the data traffic at a physical layer for distribution to at least two of the plurality of destination devices associated with the physical layer links.

Abstract: A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit. The circuit further includes a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal. The switching circuit is operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal. Between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit.

Abstract: A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes a digital filter that receives a series of digital samples and provides a filtered output. The filtered output is provided to a data detector that performs a data detection on the filtered output to create a detected output. A first summation element subtracts the filtered output from the detected output to create an error signal, and a second summation element subtracts the error signal from the filtered output to create a wander basis signal. A baseline correction feedback circuit receives the wander basis signal and provides a wander compensation signal. A derivative of the wander compensation signal is provided as feedback to the digital filter.

Abstract: A software-based development tool is operative to automatically determine an appropriate simulation configuration for a multistage switch fabric or other multiple circuit element electronic system. The development tool includes an interface permitting user control of one or more configurable parameters of the electronic system, and automatically generates a simulation configuration for the electronic system based on current values of the configurable parameters. The simulation configuration is advantageously generated without requiring further user input, and specifies interconnections between the circuit elements which satisfy the current values of the configurable parameters.

Abstract: In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimiz

Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.

Abstract: In one embodiment, defects are detected on the face of a hard-disk drive platter. A preamble, a sync mark, user or pseudorandom data, and a data pad are written to every sector on a track of the platter. Inter-sector gaps that separate consecutive sectors are overwritten with a fixed data pattern such that consecutive sectors are in phase lock with one another. After the track has been written, the track is read back and analyzed. Consecutive sectors are analyzed continuously without stopping. The preambles, sync marks, data pads, and overwritten inter-sector gaps are analyzed using suitable flaw-scan techniques. The user or pseudorandom data is analyzed using both data-integrity checks and suitable flaw-scan techniques. This process is repeated for all tracks on the disk, and defect detection is completed when all tracks have been analyzed.

Abstract: A dedicated wireless data connection to the Internet through which digital broadcasts are streamed to mobile devices specifically designed to receive and play the content of the broadcasts. A user is supplied with a hand-held mobile terminal device specifically designed for the reception and playback of Internet radio wirelessly and the content available to the user of the device is automatically pre-specified based upon the connection node with which the device is currently communicating. The device creates and maintains a wireless connection to the Internet through any existing access technology (e.g., cellular or Wi-Fi access technology), manages the connection, including roaming, and buffers data in order to present a continuous stream of content to the end-user. Using this model, local advertisers and/or stations can pay the wireless service provider to have their content broadcast in a particular region, thereby enabling regional advertising to be delivered to listeners.

Abstract: An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test bus between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies.

Abstract: A method and apparatus for improving the thermal conductivity of a circuit board (CB) assembly comprising an integrated circuit (IC) die mounted on a CB. A high thermal conductivity device is attached on a first end to a surface of the die. When the die is mounted on the CB, a void formed in the CB receives a second end of the HTC device, and the second end of the HTC device comes into contact with a portion of the CB. During operation of the die, heat produced by the die is dissipated through the HTC device and into the CB.

Abstract: A network device comprises a plurality of lookup tables and a processor. Each of the plurality of lookup tables comprises a plurality of table inputs that are associated with a plurality of processor instructions. The processor is operative to perform a network operation on a packet of data comprising a plurality of protocol header fields at least in part by performing one or more lookup cycles. A lookup cycle comprises the addressing of one of the plurality of lookup tables with one of the plurality of table inputs and the performing of the processor instruction associated with that table input. At least one of the plurality of processor instructions in the plurality of lookup tables comprises an instruction directing that the content of one of the plurality of protocol header fields be read and that one of the plurality of lookup tables be addressed with that content as the table input.

Abstract: A secondary satellite radio or broadcast channel is used to broadcast advertisement clips (e.g., audio clips) to a receiver for subsequent decoding and playback. The receiver is configured for different tiers of service, e.g., one that delivers substantially advertising-free content and another that delivers content that includes more significant amounts of advertising. The content delivered to both is the same content; however, for the service tier that includes more advertising, the advertisements broadcast on the secondary channel are interleaved into the content, preferably in such a way that the continuity of the content being delivered is not compromised.