Abstract: In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.

Abstract: Methods and apparatus are disclosed for increased pre-emphasis for clock-like data patterns to compensate for channel distortions. One aspect of the invention compensates for channel distortions by evaluating a data pattern to be transmitted; determining if the data pattern satisfies one or more predefined criteria defining a clock-like data pattern; and generating a pre-emphasis level for the clock-like data patterns that is higher than a pre-emphasis level for the data patterns that do not satisfy the one or more predefined criteria. For example, a predefined window size can be defined for determining if the data pattern satisfies the one or more predefined criteria defining the clock-like data pattern. In one exemplary implementation, the higher pre-emphasis level is generated for one or more predefined data patterns. A table can optionally be accessed to determine the pre-emphasis level based on the data pattern.

Abstract: A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. Path differences are computed between paths through a multiple-step trellis, wherein a first path is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period.

Abstract: Methods and systems are provided for estimating the DC offset distortion in a receiver. A fast Fourier transform is applied to at least a portion of a preamble portion of the received signal; an impact of the DC offset distortion on one or more empty subcarriers is determined; individual DC estimates are derived based on each of the determinations; and each of the individual DC estimates are combined to obtain an overall DC estimate.

Abstract: Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide systems for on-the-fly estimation of write pre-compensation values. Such systems include a magnetic storage medium, a read/write head assembly disposed in relation to the magnetic storage medium, and an analog to digital converter that receives an analog signal from the read/write head assembly corresponding to a data set stored on the magnetic storage medium and provides a series of digital samples corresponding to the data set. The storage devices further include a read data processing circuit that receives the same series of digital samples and provides a user data output, and a pre-compensation value calculation circuit that receives the series of digital samples and provides an updated write pre-compensation value.

Abstract: In one embodiment, the invention provides a method for accessing a physical storage-device array comprising a plurality of storage devices. The method includes (1) obtaining at least one parameter from a profile selected from two or more profiles concurrently defining two or more virtual arrays, each profile defining (i) a different virtual array associated with a corresponding set of storage devices and (ii) a parameter set of one or more parameters used for accessing the virtual array; and (2) generating an instruction, based on the at least one parameter, for accessing, or disallowing access to, information in the virtual array defined by the selected profile, wherein a parameter in each the parameter set defined by each profile indicates whether two or more storage devices in the corresponding virtual array are degraded.

Abstract: Methods and apparatus are provided for reducing power fluctuations during preamble training in a multiple antenna communication system using cyclic delays. A preamble having a legacy portion and a high throughput portion is transmitted (or received) on each of N antennas, wherein at least a portion of the preamble on a first of the N antennas is delayed relative to at least the portion of the preamble on a second of the N antennas, wherein the delay is non-orthogonal amount to introduce variation across the preambles transmitted on the N transmit antennas. The legacy portion may be, for example, an 802.11 a/g preamble.

Abstract: A method for seamless noise suppression on wideband to narrowband cell switching is described. In one embodiment the method includes applying noise suppression to a telephone signal using a first noise suppressor while operating a telephone in a first operating mode, the first noise suppressor generating an estimate of a noise components of the telephone signal; switching the telephone from the first operating mode to a second operating mode; providing the estimate of the noise component as an input to a second noise suppressor different from the first noise suppressor, when the switching step is performed; and applying noise suppression to the telephone signal using the second noise suppressor by using the estimate of the noise component provided by the first noise suppressor when the switching step is performed.

Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: A method for extending a tracking range of a PLL includes the steps of: establishing an initial tracking window of the PLL, the tracking window having a first width associated therewith; and dynamically adjusting the tracking window of the PLL within an extended tracking range when a frequency of an input signal supplied to the PLL is outside of the tracking window, the extended tracking range having a second width associated therewith which is greater than the first width.

Abstract: An inductor device in an integrated circuit includes a first winding portion, a bridge portion and a second winding portion. The integrated circuit has a first, a second, a third and a fourth metallization level. The first winding portion comprises a first metal line formed on the first metallization level and a second metal line formed on the second metallization level, the first metal line being electrically connected in parallel with the second metal line. The bridge portion comprises a third metal line formed on the third metallization level and a fourth metal line formed on the fourth metallization level, the third metal line being electrically connected in parallel with the fourth metal line. The second winding portion comprises a fifth metal line formed on the first metallization level and a sixth metal line formed on the second metallization level, the fifth metal line being electrically connected in parallel with the sixth metal line.

Abstract: A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.

Abstract: The present invention provides systems and methods for detecting a media defect. A circuit providing a hard output and a soft output is used with the hard output and the soft output being combined and the product compared with a threshold. Based at least in part on the comparison, a media defect may be identified.

Abstract: In accordance with exemplary embodiments, a Fast Fourier Transform (FFT) architecture includes elements that perform a radix-2 FFT butterfly in one processor clock cycle at steady state. Some exemplary implementations of the FFT architecture incorporate register and data path elements that relieve memory bandwidth limitations by pairing operands consumed by and results generated by two adjacent butterflies in the overall N-point FFT operation.

Abstract: A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal.

Abstract: Methods and apparatus for testing adaptive timing characteristics of a packet-based timing protocol are provided. A packet delay variation test sequence is applied to packet-based traffic as the packet-based traffic passes through a packet delay variation generator during transmission between nodes. Adaptive timing characteristics at a node that receives the packet-based traffic are evaluated in accordance with the packet delay variation test sequence.

Abstract: Embodiments of the invention include a system for entering end user information into an electronic device. The system includes a display unit with a touchscreen having a plurality of locations. The touchscreen is configured to detect the presence of an end user object proximal to one of the touchscreen locations and to detect when an end user object makes contact with one of the touchscreen locations. The system also includes a controller configured to generate an audible sound indicative of the touchscreen location to which an end user object is proximal in response to the display unit detecting the presence of the end user object proximal to the touchscreen location. The controller also is configured to generate contact location information indicative of the touchscreen location with which an end user object makes contact in response to the display unit detecting the contact of the end user object on the touchscreen location.

Abstract: One embodiment monitors a line-side electrical current provided by a power sourcing equipment (PSE) port to a powered device (PD), the PSE port having a power-isolation transformer with a primary coil on an isolated side and a secondary coil on a line side. A switching signal having a switching period and a duty cycle is applied to the primary coil of the power-isolation transformer. A value is determined for an electrical current on the isolated side of the power-isolation transformer, conversion is performed between a line-side electrical current value Iout and a corresponding isolated-side peak-current value Ipeak, and the line-side electrical current is indirectly monitored based on the determined isolated-side current value.

Abstract: Methods and apparatus are provided for clock skew calibration in a clock and data recovery system. One aspect of the invention compensates for skew among a plurality of clocks in a clock and data recovery system. The clocks are applied to a plurality of latches to sample an incoming signal. A reference signal, such as a Nyquist signal, is applied to a data input of each of the latches. Statistics of “early” and “late” corrections applied to at least one of the clocks by a bang-bang phase detector in the clock and data recovery system are evaluated and a delay of a clock buffer associated with the at least one clock is adjusted to obtain approximately a 50% early-to-late ratio for the at least one clock. The clock and data recovery system ensures that the early-to-late ratio for the sum of the plurality of clocks is approximately 50%.

Abstract: A clock generator is provided for a transmitter in a transceiver adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit recovers a receive clock signal and outputs a reference clock signal. The clock generator includes a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock outputs a local clock signal. The frequency difference detector outputs a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer outputs a transmit clock signal having a same frequency as the recovered receive clock signal.