Abstract: Various systems and methods for code based error reduction. For example, in one digital information system including a channel detector and a decoder, the channel detector receives an encoded data set and is operable to perform a column parity check. The channel detector provides an output representing the encoded data set. The decoder receives the output from the channel detector and is operable to perform two checks. The two checks may be one of: two pseudo-random parity checks, a pseudo-random parity check and a slope parity check, and two slope parity checks. In addition, the decoder provides another output representing the encoded data set.

Abstract: Virtual concatenation circuitry is disclosed for implementation in a network element of a data communication network. The virtual concatenation circuitry in a preferred embodiment is operative: (i) to maintain, for each of the individual member streams of a virtual concatenation stream, a corresponding counter which tracks pointer adjustments for that member stream; and (ii) to generate pointers based on values of the counters so as to substantially equalize incoming and outgoing pointer adjustments for the member streams at the network element.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply. The circuit includes a PVT detector configured to generate a control signal and an adjustable resistance device configured to adjust its resistance in response to the control signal.

Abstract: Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.

Abstract: A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC.

Abstract: In one embodiment, the present invention is a framer/mapper/multiplexor (FMM) device that can simultaneously (i) send protection copies of both its working incoming high-speed (e.g., STS-12) signal and incoming low-speed signals to a protection FMM device, and (ii) receive corresponding protection signals from the protection FMM device. Furthermore, the FMM device can select between working and protection signals at a switching level (e.g., STS-1) lower than the high-speed level, allowing for 1+1 APS/MSP protection and equipment protection at the board level, the device level, and at the STS-1 level. Yet further, four or more FMM devices can be configured so that all FMM devices can communicate with their corresponding protection FMM devices using a single, shared, 4-pin link (e.g., quad-OC-3 mode), and still select between working and protection signals at the switching level (e.g., STS-1).

Abstract: A digital modulation system provides enhanced multipath performance by using modified orthogonal codes with reduced autocorrelation sidelobes while maintaining the cross-correlation properties of the modified codes. For example, the modified orthogonal codes can reduce the autocorrelation level so as not to exceed one-half the length of the modified orthogonal code. In certain embodiments, an M-ary orthogonal keying (MOK) system is used which modifies orthogonal Walsh codes using a complementary code to improve the auto-correlation properties of the Walsh codes, thereby enhancing the multipath performance of the MOK system while maintaining the orthogonality and low cross-correlation characteristics of the Walsh codes.

Abstract: A binaural cue coding scheme in which cue codes are derived from the transmitted audio signal. In one embodiment, an encoder downmixes C input channels to generate E transmitted channels, where C>E>1. A decoder derives cue codes from the transmitted channels and uses those cue codes to synthesize playback channels. For example, in one 5-to-2 BCC embodiment, the encoder downmixes a 5-channel surround signal to generate left and right channels of a stereo signal. The decoder derives stereo cues from the transmitted stereo signal, maps those stereo cues to surround cues, and applies the surround cues to the transmitted stereo channels to generate playback channels of a 5-channel synthesized surround signal.

Abstract: A method and system for analyzing simulated packet delay variation (PDV) using derivative PDV is disclosed. The delay-step method for simulating PDV determines a delay for each packet in a stream of packets generated at a regular interval. Delay target values are randomly selected based on a statistical distribution, such as a Gaussian distribution. Delay-steps are determined for each packet based on the delay target values. The delay-steps can be fixed or variable sized steps which are used to adjust the delay of sequential packets. PDV is generated by delaying each of the packets with the delay determined for that packet. The derivative PDV is calculated to evaluate a delay rate of change on a packet-by-packet basis. The derivative PDV can be used as a metric to specify stresses for adaptive packet timing recovery stress testing.

Abstract: Generally, methods and apparatus are provided for deriving an integrated circuit (IC) clock signal with a frequency that is offset from the IC system clock. An offset clock having a frequency that is offset from a system clock is generated by configuring a ring oscillator in a first mode to generate the system clock having a desired frequency; and adjusting the configuration of the ring oscillator in a second mode to generate the offset clock having the frequency that is offset from the system clock. The configuration of the ring oscillator is adjusted in the second mode by adjusting (i) a power supply value applied to the ring oscillator in the second mode relative to a power supply value applied in the first mode; or (ii) a number of delay line elements that are active in the ring oscillator loop.

Abstract: A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.

Abstract: Methods and apparatus are provided for compensating for skew in a differential signal using non-complementary inverters. A skew attenuator is provided for a differential signal having a P rail and an N rail. The skew attenuator comprises one or more non-complementary inverters for compensating for skew between the P rail and the N rail. The non-complementary inverters attenuate a time difference of arrival of transitions for the P rail and the N rail. An exemplary skew attenuator includes a first non-complementary inverter associated with each of the P rail and the N rail. The P rail and the N rail signals are each applied to a gate of one of the first non-complementary inverters, and drains of the first non-complementary inverters provide differential output signals OUTP and OUTN. The exemplary skew attenuator also includes an additional non-complementary inverter associated with each of the first non-complementary inverters.

Abstract: A wireless piconet network device includes a GPS receiver to determine and provide earth coordinates to a gatekeeper of a wireless network so as to provide a level of security to wireless networks which requires accessing wireless devices to be within predefined boundary coordinates. The automatic restriction of access to a wireless network (e.g., a wireless local area network (LAN) such as a piconet network) by requiring a wireless network device to provide earth coordinates (e.g., GPS location information) as part of an establishment or maintenance of a connection to a wireless network, independent of a range of communication of any device in the wireless network. A wireless piconet network device outside of predetermined earth coordinates of a secured area (e.g., a building, a room in a building, a desk in a room in a building, etc.

Abstract: A mobile communication device, in particular a mobile telephone, a PDA or a MDA. In one embodiment, the mobile communication device includes: (1) a main body and (2) a camera module, coupled to the main body and configured for rotation relative to the main body about at least one axis of rotation. In another embodiment, the main body has a camera module mechanical interface, the camera module has a main body mechanical interface that is complementary to the camera module mechanical interface and the camera module is configured to be removably coupled to the main body and further configured for rotation relative to the main body about at least one axis of rotation.

Abstract: A self calibrating network comprises a first node and a second node. The first node transmits a calibration data packet. The second node receives the calibration data packet and determines a calibration value for the second node to optimize the transfer of data from the first node to the second node.

Abstract: A method of restricting operation of at least one electrical device connectable to a site electrical power supply system and an electrical device and transmitting device for operating in accordance with the method. In one embodiment, the method includes: (1) receiving a signal including a site identification code via the site electrical power supply system and extracting the site identification code by the at least one electrical device, (2) determining a correspondence between the site identification code and a site confirmation code stored in a memory of the at least one electrical device and (3) allowing unrestricted operation of the at least one electrical device only when the site identification and site confirmation codes correspond.

Abstract: A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

Abstract: Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.

Abstract: A method and system for providing connectionless configurations for stress testing timing and synchronization in data packet networks. Packet traffic of interest is transmitted through multiple interconnected switching nodes such that different packets can be transmitted over different paths through the switching nodes. The nodes can support background traffic in order to generate delays for the packets at each of the switching nodes. By allowing packets to use multiple paths in a single testing configuration, a connectionless packet flow can be utilized for adaptive packet timing recovery stress testing.

Abstract: Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.