Abstract: In a communication system comprising a mapper or other type of physical layer device coupled to a link layer device, the physical layer device comprises payload extraction circuitry and payload insertion circuitry. The payload extraction circuitry is configured to extract a payload from an ingress synchronous transport signal received over an ingress link, and the payload insertion circuitry is configured to insert a payload received from the link layer device into an egress synchronous transport signal for transmission over an egress link. The payload extracted from the ingress synchronous transport signal is transmitted by the physical layer device to the link layer device over an output serial data line of a serial interface, and the payload inserted into the egress synchronous transport signal is received by the physical layer device from the link layer device over an input serial data line of the serial interface.

Abstract: A technique to reduce refresh power in a DRAM. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a refresh controller that generates a refresh address and controls the refresh of the memory cells addressed by the refresh address. A marker memory is used by the refresh controller to determine which of the memory cells requires refreshing at a rate faster than the refresh rate of the remaining memory cells. Testing the DRAM uses a method to determine which of the memory cells are to be refreshed at the faster rate and to store the results in the marker memory.

Abstract: Methods and apparatus are provided for per-antenna training in a multiple antenna communication system having a plurality of transmit antenna branches. A long training sequence is transmitted on each of the transmit antenna branches such that only one of the transmit antenna branches is active at a given time. The active transmit antenna branch transmits the long training sequence with an increased power level relative to a transmission of a payload by the active transmit antenna branch. The increased power level for the active transmit antenna branch compensates for the inactive transmit antenna branches being silent during the given time. Thus, the active transmit antenna branch provides approximately the same antenna power while transmitting the long training sequence as a total power of the plurality of transmit antenna branches during a transmission of the payload. The increased power level can be provided, for example, by a digital-to-analog converter associated with the active transmit antenna branch.

Abstract: A buffer circuit for use in a digital communication system includes a memory and a controller coupled to the memory. The memory is configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system. The controller is operative to store data from the first data stream into corresponding timeslots in the memory in a first order, to individually adjust delays of the respective timeslots as a function of respective delay control parameters, and to generate a second data stream by reading the timeslots stored in the memory in a second order.

Abstract: Methods and apparatus are provided for adjusting receiver gain based on received signal envelope detection. The gain of a received signal is adjusted by obtaining a plurality of samples of the received signal for a given unit interval; determining an amplitude of the received signal based on the samples; and adjusting a receiver gain based on the determined amplitude. The received signal can be sampled, for example, using a plurality of latches. The value of the received signal can then be estimated by evaluating one or more of the latch values. Once the amplitude of the received signal is determined, one or more latches can be positioned at a desired target amplitude and the receiver gain can be adjusted until the amplitude of the received signal is within a desired tolerance of the specified target value.

Abstract: In a preferred embodiment, a battery charging system in the form of an integrated circuit (IC), incorporated in a consumer electronic device, has a charging controller, a charging current generator, a junction temperature sensor, and a device current monitor. The junction temperature sensor provides to the charging controller a measured junction temperature of the IC. The charging current generator utilizes fractional synthesis, which involves regulating the duty cycles of multiple current sources, to achieve increased current resolution. The charging controller regulates the charging current provided by the charging current generator based on the relation of the measured junction temperature to three or more threshold temperatures.

Abstract: Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management controller. The power management controller is operable to apply power to one of the clock sources and to select another of the clock sources for synchronization of the circuit. Then, upon stabilization of the first clock source, it is selected by the power management controller to synchronize the circuit.

Abstract: Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude.

Abstract: Various systems and methods for clock generation are disclosed herein. As just one example, a system for clock generation is disclosed that includes a phase/frequency control circuit that provides a feedback control; a multi-range selector circuit that receives the feedback control; and a controlled oscillator that provides an output with a phase and frequency at least in part governed by the multi-range selector circuit and the feedback control. In various instances of the aforementioned embodiments, the controlled oscillator is a ring oscillator relying on inherent capacitance.

Abstract: A method includes storing video data in a disk by way of a first queue comprising a linked list of buffers. Video data are received into the first queue by way of a tail buffer. The tail buffer is at one end of the linked list of buffers in the first queue. Video data are copied from a head buffer to the disk. The head buffer is at another end of the linked list of buffers in the first queue. The video data are displayed in real-time directly from the buffers in the queue, without retrieving the displayed video data from the disk, and without interrupting the storing step.

Abstract: In one embodiment, a transmitter (a) caches one or more MAC-d PDUs received from a network layer, (b) selects a subset of the MAC-d PDUs for combination into a MAC-e PDU, (c) generates the MAC-e PDU from the subset of selected MAC-d PDUs, (d) caches a data structure to allow re-generation of the MAC-e PDU, wherein the re-generation does not rely on any cached copy of the MAC-e PDU, (e) transmits the MAC-e PDU for receipt by a receiver; and (f) determines whether an ACK was received, wherein if an ACK was not received, then the MAC-e PDU is re-generated using the cached data structure and the subset of selected MAC-d PDUs, and steps (e) and (f) are repeated, and if an ACK was received, then the memories used to cache the data structure and the first subset of MAC-d PDUs are freed.

Abstract: In one embodiment, the present invention is a framer/mapper/multiplexor (FMM) device that can simultaneously (i) send protection copies of both its working incoming high-speed (e.g., STS-12) signal and incoming low-speed signals to a protection FMM device, and (ii) receive corresponding protection signals from the protection FMM device. Furthermore, the FMM device can select between working and protection signals at a switching level (e.g., STS-1) lower than the high-speed level, allowing for 1+1 APS/MSP protection and equipment protection at the board level, the device level, and at the STS-1 level. Yet further, four or more FMM devices can be configured so that all FMM devices can communicate with their corresponding protection FMM devices using a single, shared, 4-pin link (e.g., quad-OC-3 mode), and still select between working and protection signals at the switching level (e.g., STS-1).

Abstract: The present invention implements a software controlled thermal feedback system for battery charging circuitry in portable devices, specifically in cellular telephones. The charging hardware block is integrated into a mixed-signal analog base-band (ABB) circuit. In addition to standard function controls, integrated within the ABB are silicon temperature sensors used to monitor the temperature of any silicon components integrated on the ABB and detect any temperature change due to thermal heating. The temperature value is passed to the digital base band (DBB) circuit. Here, a microcontroller is programmed to perform power management functions relating to the ABB. Thermal control software, implemented on the DBB microcontroller, monitors the silicon temperature of the ABB and adjusts the power levels on the ABB accordingly to provide a controlled chip temperature.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and preceding the encoded information. The preceding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

Abstract: Various embodiments of a hybrid class AB super follower circuit are provided.

Abstract: The present invention implements an apparatus for correcting duty cycle distortion in high speed clock signals. The apparatus includes delay cells that delay each of first and second differential initial clock signals. The apparatus further includes a latch that generates an output clock signal based on the delayed first and second differential initial clock signals. The apparatus further includes a differential feedback buffer that converts the output clock signal into first and second differential feedback signals. The apparatus further includes a feedback circuit that adjusts the delay cells based on the first and second differential feedback signals.

Abstract: An improved method and apparatus for setting a trip-point temperature value for detection of an over-temperature condition in a chip when a reading from a main temperature sensor exceeds the trip-point temperature value. In one embodiment, the trip-point temperature value is set to a known temperature limit value offset by a temperature difference, ?T. ?T is calculated by taking the difference between a reading of the main temperature sensor and a reading of another temperature sensor, remote from the main temperature sensor, while a heat-generating circuit is enabled. The main temperature sensor is distal from heat-generating circuit on the chip and the remote temperature sensor is proximate the heat-generating circuit. For multiple heat-generating circuits on the chip, a ?T is determined for each of the heat-generating circuits, and the largest ?T is used to calculate the trip-point temperature value. Advantageously, the largest ?T determination may be done only once.

Abstract: A buffer circuit uses (e.g., active) inductors for driving capacitive loads. In one embodiment, the buffer circuit has one or more stages, each stage having one CMOS inverter. Each CMOS inverter has one NMOS transistor and one PMOS transistor and is coupled to a stage input and a stage output. Additionally, at least one stage of the buffer circuit has two inductors, each coupled between a different voltage reference for the buffer circuit and the stage output. One inductor has a PMOS transistor coupled to the gate of an NMOS transistor and the other inductor has an NMOS transistor coupled to the gate of a PMOS transistor. When driving capacitive loads, the inductors partially tune out the apparent load capacitance CL, thereby improving the charging capabilities of inverter and enabling quicker charge and discharge times. Furthermore, partially tuning out apparent load capacitance facilitates the driving of larger capacitive loads.

Abstract: Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.

Abstract: An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface characterized by the same level of planarity as the dielectric material upper surface. In certain embodiments, the upper surface of the conductive layer is substantially coplanar with the dielectric material upper surface.