Patents Assigned to Analog Devices Global
  • Patent number: 10338132
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 2, 2019
    Assignee: Analog Devices Global
    Inventors: Edward John Coyne, Alan J. O'Donnell, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Thomas G. O'Dwyer, David Aherne, Michael A. Looby
  • Patent number: 10338224
    Abstract: A system and method for operating a high dynamic range analog front-end receiver for long range LIDAR with a transimpedance amplifier (TIA) include a clipping circuit to prevent saturation of the TIA. The output of the clipping circuit is connected via a diode or transistor to the input of the TIA and regulated such that the input voltage of the TIA remains close to or is only slightly above the saturation threshold voltage of the TIA. The regulation of the input voltage of the TIA can be improved by connecting a limiting resistor in series with the diode or transistor. A second clipping circuit capable of dissipating higher input currents and thus higher voltages may be connected in parallel with the first clipping circuit. A resistive element may be placed between the first and second clipping circuits to further limit the input current to the TIA.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: July 2, 2019
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Yalcin Alper Eken, Alp Oguz
  • Patent number: 10340700
    Abstract: According to some aspects, a power regulation system for energy harvesters that lacks a battery is provided. In some embodiments, the power regulation system may receive power from multiple energy harvesters that generate energy from different sources, such as wind currents and ambient light. In these embodiments, the power regulation system may selectively provide power from one or more of the energy harvesters to a load as environmental conditions change and power itself with energy from the energy harvesters. Thereby, the power regulation system may start and operate without a battery and provide power to the load over a wider range of environmental conditions.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: July 2, 2019
    Assignee: Analog Devices Global
    Inventors: Junifer Frenila, Perryl Glo Angac, Oliver Silvela, Jr.
  • Publication number: 20190195825
    Abstract: An electrochemical sensor is provided which may be formed using micromachining techniques commonly used in the manufacture of integrated circuits. This is achieved by forming microcapillaries in a silicon substrate and forming an opening in an insulating layer to allow environmental gases to reach through to the top side of the substrate. A porous electrode is printed on the top side of the insulating layer such that the electrode is formed in the opening in the insulating layer. The sensor also comprises at least one additional electrode. The electrolyte is then formed on top of the electrodes. A cap is formed over the electrodes and electrolyte. This arrangement may easily be produced using micromachining techniques.
    Type: Application
    Filed: August 29, 2017
    Publication date: June 27, 2019
    Applicant: ANALOG DEVICES GLOBAL
    Inventors: Alfonso Berduque, Helen Berney, William Allan Lane, Raymond J. Speer, Brendan Cawley, Donal McAuliffe, Patrick Martin McGuinness
  • Patent number: 10333543
    Abstract: Techniques that allow application of noise-shaped dither without applying dither at sampling, resulting in the analog-to-digital converter (ADC) circuit advantageously being balanced during acquisition. Balancing the ADC circuit at acquisition can reduce the risk of sampling digital interferences that can couple in through the references or substrates.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 25, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Christopher Peter Hurrell, Hongxing Li, Colin G. Lyden
  • Publication number: 20190182445
    Abstract: Embodiments of the present disclosure provide ADCs particularly suitable for PDAF image sensors, which ADCs may have an increased speed and/or reduced design complexity and power consumption compared to conventional implementations. An example ADC for a PDAF image sensor is configured to implement modified SAR techniques which reduce the number of bit trials required for conversion, and enable increased number of samples in a row-conversion time period of the image sensor. The ADC may implement the modified SAR techniques in combination with CMS in pixel readout signal chain, which may reduce noise without a proportionate increase in ADC sample rate.
    Type: Application
    Filed: September 11, 2018
    Publication date: June 13, 2019
    Applicant: Analog Devices Global Unlimited Company
    Inventors: Daniel Peter CANNIFF, Edward C. GUTHRIE, Jonathan Ephraim David HURWITZ
  • Patent number: 10320340
    Abstract: Various examples are directed to a digital predistortion (DPD) circuit comprising a DPD actuator circuit, a DPD feedback frequency-shaping filter, a basis matrix generator circuit, a basis matrix frequency-shaping filter, and a DPD adaption circuit. The DPD actuator circuit may generate a predistorted signal based at least in part on an input signal and a set of frequency-shaped DPD parameters. The DPD feedback frequency-shaping filter may filter a DPD feedback signal to generate a frequency-shaped DPD feedback signal. A passband of the DPD feedback frequency-shaping filter may include substantially all of a bandwidth of the input signal and exclude a distortion term outside the bandwidth of the input signal. The basis matrix generator may generate a basis matrix based at least in part on a power amplifier feedback signal The basis matrix frequency-shaping filter may generate a frequency-shaped basis matrix based at least in part on the basis matrix.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 11, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Patrick Pratt, David Jennings
  • Patent number: 10320280
    Abstract: An LC filter circuit reduces an output voltage ripple of a switching power supply using coupled inductors in combination with a capacitor to form a notch filter, and aligning the notch region of the notch filter with a ripple frequency of the switching power supply to attenuate the frequency region of the fundamental ripple frequency by a larger amount than other frequencies.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 11, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Aldrick S. Limjoco, Jefferson Albo Eco
  • Patent number: 10320407
    Abstract: A system having two or more sensing nodes coupled to a control node using a serial communication channel having separate transmit and receive circuits, where each sensing node includes an ADC circuit and a microcontroller, operation of the ADC circuit in each sensing node is concurrently synchronized by the control node using the transmit circuit (e.g., with respect to the control node) of the serial communication channel. The control node can synchronize operation of two or more ADC circuits in separate sensing nodes without using shared clocks or other control signals.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: June 11, 2019
    Assignee: Analog Devices global Unlimited Company
    Inventor: Narsimh Dilip Kamath
  • Patent number: 10312902
    Abstract: This application discusses techniques for providing a power-on reset (POR) circuit. The techniques take advantage of the small size of active devices, consume very little current and can use a native NMOS transistor to provide a stable reference over temperature and voltage variations.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: June 4, 2019
    Assignee: Analog Devices Global
    Inventors: Amit Kumar Singh, Sriram Ganesan
  • Patent number: 10310539
    Abstract: The present disclosure relates to a PTAT voltage reference circuit and a temperature independent voltage reference circuit in which the effect of transistor base currents on the circuit output is compensated for. This is achieved by a pair of compensation resistors. The base current from one of the pair of transistors is used to increase the voltage drop across one of the compensation resistors. The base current from the other of the pair of transistors is used to decrease the voltage drop across another of the compensation resistors, by an equal amount. The compensation resistors are connected in series with the resistor which reflects the difference in base-emitter voltage (?VBE). The circuit output is measured across the series connected resistors. As such, the base currents are compensated for at the output.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: June 4, 2019
    Assignee: ANALOG DEVICES GLOBAL
    Inventor: Stefan Marinca
  • Patent number: 10310476
    Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 4, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Navdeep Singh Dhanjal, Shengbing Zhou
  • Patent number: 10312926
    Abstract: Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power. Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: June 4, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventor: Roberto Sergio Matteo Maurino
  • Patent number: 10309803
    Abstract: Sensor error detection with an additional channel is disclosed herein. First and second magnetic sensing elements can be disposed at angles relative to each other. In some embodiments, the first and second magnetic sensing elements can be magnetoresistive sensing elements, such as anisotropic magnetoresistance (AMR) sensing elements. Sensor data from first and second channels, respectively, having the first and second sensing elements, can be obtained. Third channel can receive a signal from the first sensing element and a signal from the second sensing element, and sensor data from the third channel can be obtained. Expected third channel data can be determined and compared to the obtained third channel data to indicate error.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 4, 2019
    Assignees: Analog Devices Global, Sensitec GmbH
    Inventors: Gavin Patrick Cosgrave, Jochen Schmitt, Dermot G. O'Keeffe
  • Patent number: 10312930
    Abstract: Techniques are provided for compensating gain of a combined amplifier and analog-to-digital converter (ADC) circuit, for example, due to additional filtering added to an input of the circuit. In an example, an integrated circuit including an amplifier and ADC can include an amplifier circuit configured to receive an input signal and to amplify the input signal based on an input resistance and a feedback resistance, and to provide an amplified representation of the input signal, and an ADC circuit configured to receive an output of the amplifier, to determine a digital coefficient associated with an additional input resistance coupled to the amplifier, and to provide a compensated digital representation of the amplified representation of the input signal using the digital compensation coefficient.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 4, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Eamonn J. Byrne, Jesus Bonache, Andrejs Tunkels
  • Patent number: 10305369
    Abstract: This application discusses techniques for reducing the energy of an output ripple in a voltage converter at a switching frequency of the voltage converter. In certain examples, an amplitude of a reference voltage can be modulated with a time-varying random value or pseudo-random value to provide a reduction in the energy of the output ripple at the switching frequency of the voltage converter.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 28, 2019
    Assignee: Analog Devices Global
    Inventors: Bin Shao, Sean Kowalik, Alan S. Walsh, Danzhu Lu
  • Patent number: 10295580
    Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: May 21, 2019
    Assignee: Analog Devices Global
    Inventors: Vamshi Krishna Chillara, Pablo Cruz Dato, Declan M. Dalton
  • Patent number: 10298276
    Abstract: Power amplifier circuits can behave in a non-linear manner particularly when operated to produce output signal swings approaching an amplifier saturation region. A pre-distortion signal can be applied to a signal to be transmitted to compensate for such power amplifier non-linearity. In applications where two or more transmitter power amplifiers are used, a beam-former can be configured to modify a digitally pre-distorted transmission signal by applying respective beam-forming weighting factors to the digitally pre-distorted transmission signal to provide input transmission signals for respective ones of the power amplifier circuits. The pre-distortion signal can be established at least in part using one or more of a sensed or estimated representation of a transmitted beam formed by spatially aggregating transmitted outputs from the two or more power amplifier circuits.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: May 21, 2019
    Assignee: Analog Devices Global
    Inventors: Patrick Pratt, Michael O'Brien
  • Patent number: 10290194
    Abstract: System and techniques for an occupancy sensor are described herein. Images from a camera can be received. Here, the camera has a certain a field of view. A proximity indicator from a proximity detector can be received when an object enters the field of view. The images from the camera are processed to provide an occupancy indication. A first technique is used for the occupancy indication in the absence of the proximity indicator and a second technique is used otherwise.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: May 14, 2019
    Assignee: Analog Devices Global
    Inventor: Akshayakumar Haribhatt
  • Patent number: 10288582
    Abstract: An integrated ion-sensitive probe is provided. In an example, an ion-sensitive probe can include a semiconductor substrate and a first passive electrode attached to the semiconductor substrate. The first passive electrode can be configured to contact a solution and to provide a first electrical voltage as function of a concentration of an ion within the solution. In certain examples, a passive reference electrode can be co-located on the semiconductor substrate. In some examples, processing electronics can be integrated on the semiconductor substrate.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: May 14, 2019
    Assignee: Analog Devices Global
    Inventors: Helen Berney, William Allan Lane, Patrick Martin McGuinness, Thomas G. O'Dwyer