Abstract: A method of and apparatus for protecting a MEMS switch is provided. The method and apparatus improve the integrity of MEMS switches by reducing their vulnerability to current flow through them during switching of the MEMS switch between on and off or vice versa. The protection circuit provides for a parallel path, known as a shunt, around the MEMS component. However, components within the shunt circuit can themselves be removed from the shunt when they are not required. This improves the electrical performance of the shunt when the switch is supposed to be in an off state.

Abstract: A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.

Abstract: Apparatus and techniques described herein can include a load circuit comprising a direct current (DC) input terminal, and a source circuit comprising a direct current (DC) output terminal coupled to the DC input terminal of the load circuit. The source circuit can include a source control circuit configured to provide a current-limited DC output voltage and monitor the current-limited DC output voltage to detect an authentication signal provided at the DC output terminal by the load circuit, the load circuit configured to modulate the voltage at the DC output terminal using a pull-down circuit. The load circuit can be configured to compare the supply voltage at the DC input terminal to a reference voltage and, in response, energize other portions of the load circuit when the input current provided the DC input terminal is sufficient as indicated at least in part by the comparison.

Abstract: Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.

Abstract: Switching interference is a primary artifact which affects the accuracy of arc detectors. To address switching interference, conventional arc detectors employ computationally intensive techniques which are often designed specifically for a target application. Thus, conventional arc detectors require a significant amount of hardware to accurately detect arc faults, which can increase costs of the power systems and prohibit wide deployment of arc detectors. With improved signal processing, a unique method for arc detection can accurately detect arc faults efficiently while tolerate switching interference from an inverter of the power system. Specifically, the method provides accurate but efficient arc detection by using a small Fast Fourier Transform with coherent sampling that is accomplished with a common clock generator in combination with signal conditioning. The overall system implementing the method is also programmable to suit a variety of target applications.

Abstract: A capacitive gain amplifier circuit amplifies an input signal by a pair of differential amplifier circuits couples in series. The first differential amplifier circuit is reset during an autozero phase while disconnected from the second differential amplifier circuit, and the first and second differential amplifier circuits are connected together in series during a chop phase. A set of feedback capacitors is selectively switched in between respective outputs of the second differential amplifier circuit and respective inputs of the first differential amplifier circuit during the chop phase.

Abstract: An adaptive self-configuring sensor node is disclosed herein. The node is associated with one or more sensor, and can include a microcontroller unit (MCU), sensors and a wired/wireless communication module (e.g., transceiver) to communicate the data collected by the sensors. Sensor node software running on the CPU can be adaptively reconfigured based on the sensors connected with the node, and using configuration data that is read from a non-volatile memory (NVM). The NVM can further store loadable sensor device specific data acquisition and processing (DAP) routines corresponding to one or more of the sensors, which can be executed to configure a sensor or cause collection or processing of sensor data.

Abstract: Techniques for fabricating low-loss magnetic vias within a magnetic core are provided. According to some embodiments, vias with small, well-defined sizes may be fabricated without reliance on precise alignment of layers. According to some embodiments, a magnetic core including a low-loss magnetic via can be wrapped around conductive coils of an inductor. The low-loss magnetic vias can improve performance of an inductive component by improving the quality factor relative to higher loss magnetic vias.

Abstract: A minimally invasive surgical instrument using 3-axis magnetic positioning, system and methods thereof. This invention describes two key ideas that enable the development of a magnetic position system based on integrated anisotropic magnetoresistive (AMR) magnetic field sensors. This achieves the resolution, power and area targets necessary to integrate 3 axes anisotropic magnetoresistance (AMR) sensors along with the Analog Front End integrated circuit (IC) in a 4 mm by 350 um integrated solution for catheter applications. The stringent area and power dissipation requirements are met by development through both system level solutions for higher field strengths and a minimally necessary Analog Front End (AFE) to meet the 1 mm rms resolution requirement in the power dissipation and area budget.

Abstract: A combined isolator and power switch is disclosed. Such devices are useful in isolating low voltage components such as control compilers from motors or generators working at high voltages. The combined isolator and power switch includes circuits to transfer internal power from its low voltage side to the switch driver circuits on the high voltage side. The combined isolator and switch is compact and easy to use.

Abstract: A magnetic device may include a magnetic structure, a device structure, and an associated circuit. The magnetic structure may include a patterned layer of material having a predetermined magnetic property. The patterned layer may be configured to, e.g., provide a magnetic field, sense a magnetic field, channel or concentrate magnetic flux, shield a component from a magnetic field, or provide magnetically actuated motion, etc. The device structure may be another structure of the device that is physically connected to or arranged relative to the magnetic structure to, e.g., structurally support, enable operation of, or otherwise incorporate the magnetic structure into the magnetic device, etc. The associated circuit may be electrically connected to the magnetic structure to receive, provide, condition or process of signals of the magnetic device.

Abstract: Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication whilst still allowing thick isolation layers to be deployed, in examples of the disclosure a pre-formed solid layer of dielectric material is bonded to the substrate over the first transformer coil or capacitive plate. The preformed solid layer is formed from a thick layer of solid dielectric material, which is ground to the required thickness, either prior to being bonded to the circuit substrate, or thereafter. Such techniques result in a thick isolation layer that is formed more quickly and with lower outgassing risk than conventional spin-coating or deposition techniques.

Abstract: Embodiments of the present disclosure provide an optical range finder that includes a transimpedance amplifier (TIA) and a photodiode emulation circuitry for testing the TIA. The photodiode emulation circuitry may be coupled to an input port of the TIA and configured to receive one or more parameters specifying one or more characteristics of a test current signal to be provided to the TIA. The photodiode emulation circuitry may further be configured to provide the test current signal in accordance with the one or more parameters to the input port of the TIA while the photodiode is also coupled to the input port of the TIA.

Abstract: Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication while still allowing thick isolation layers to be deployed, in examples of the disclosure pre-formed sheets or tapes of dielectric material are applied to the substrate over the first transformer coil or capacitive plate, for example by being rolled onto the substrate using a heated roller. Such a technique results in a thick isolation layer that is formed using a simple process and much more quickly and reliably than conventional spin-coating or deposition techniques.

Abstract: Current transducers are widely used in current measuring systems. They provide good isolation between the supply voltage and the measurement equipment. However they can introduce small phase errors which can become significant sources of error if the current to a load is out of phase with the supply voltage for the load. This disclosure discusses a robust measurement apparatus and method that can be used in situ to monitor for and correct phase errors.

Abstract: Apparatus and methods for compensating radio frequency (RF) transmitters for local oscillator (LO) leakage are provided herein. In certain configurations herein, a transmitter generates an RF transmit signal based on mixing an input signal with an LO signal. Additionally, the transmitter is calibrated to compensate for LO leakage, which provides a number of benefits, including lower levels of undesired emissions from the transmitter.

Abstract: Aspects of this disclosure relate to active antenna calibration. In some embodiments, a local oscillator signal can be injected into the receive path for misalignment measurement and calibration of the receive path, a transmit signal from a transmit path can be coupled to a receive path, and the transmit path can be calibrated relative to the receive path.

Abstract: Techniques are described to cancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.

Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.

Abstract: Systems and methods to reduce the amount of reference current drawn by a SAR ADC by including an auxiliary or precharge reference source. The ADC can connect the bit trial capacitors of a main digital-to-analog converter (DAC) to an auxiliary or precharge reference source during the loading of the bit trials, and then the ADC can switch to a main reference buffer. After allowing enough time for both phases, the main DAC can proceed with the bit trials to resolve the remaining bits. The rest of the bit trials can be performed directly using the main reference buffer.