Abstract: A communication unit comprises a plurality of antenna element feeds (203, 205) for coupling to a plurality of antenna elements of an antenna array, where each antenna element feed comprises at least one coupler; and a plurality of transmitters operably coupled to the plurality of antenna element feeds. At least one transmitter of the plurality of transmitters comprises: an input for receiving a first signal and at least one second signal; beamformer logic arranged to apply independent beamform weights (RefBF1, RefBF2) on the first signal and the at least one second signal of the transmitter respectively, wherein each of the independent beamform weights is allocated on a per sector basis; and a signal combiner arranged to combine the first signal and the second signal to produce a combined signal, such as that the combined signal supports a plurality of sectored beams.

Abstract: The amplifier circuit includes a pair of differential input stages coupled to an output stage where both a selected input stage and an unselected input stage are active with one of either a differential input signal or a reference voltage. A switching network couples a first input differential signal to a first differential input stage and a reference voltage to a second differential input stage when an amplifier input signal is less than a threshold voltage. The switching circuit also couples the second input differential signal to the second differential input stage and the reference voltage to the first differential input stage when the amplifier input signal is greater than the threshold signal.

Abstract: Embodiments of the present disclosure propose analog-to-digital conversion (ADC) systems particularly suitable for Light Detection and Ranging (LIDAR) implementations. An exemplary proposed ADC system is configured to determine whether an absolute value of an analog value is greater than a threshold, and, upon positive determination, assign a predetermined digital value as a digital value corresponding to the analog value, without proceeding with the analog-to-digital conversion of the analog value. Because the ADC system only proceeds with the analog-to-digital conversion, using an ADC, when the input analog value is smaller than the threshold, and otherwise the input analog value is simply assigned some predefined digital value, design complexity and power consumption of the system may be significantly reduced, compared to conventional ADCs used in LIDAR applications.

Abstract: According to a first aspect of this disclosure there is provided a voltage controlled current path. The voltage controlled current path comprises a first stage arranged to conduct current once the voltage at an input node of the first stage exceeds a threshold value. The amount of current that passes through the first stage is a function of the voltage at the input node. A second stage is arranged to pass a current that is a function of the current passing through the first stage.

Abstract: The present disclosure provides a voltage variable attenuator (VVA) with a controllable matching network. The output of the attenuation portion of the VVA is couple to a matching network. The matching network includes a resistive element, which may be a Field Effect Transistor (FET), whose resistance may be controlled as a function of attenuation. In particular, a control voltage used to control the resistance of the attenuation portion of the VVA is also used to control the resistive element of the matching network. In this manner, the output impedance of the VVA may be maintained at a desired level.

Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.

Abstract: Thin film resistive sensors typically include a number of resistive components. These components should be well matched in order for the sensor to provide accurate readings. When a sensor is incorporated within an integrated circuit, the resistive components may be formed over, or under, metallic traces that form part of other components. As a result, the thin film resistive components are subjected to different levels of stress. This disclosure provides a structure that is arranged to mitigate the effects of stress.

Abstract: Embodiments of full duplex radios are disclosed herein. For example, a radio may include: a first transmitter, a second transmitter, and a receiver. The first transmitter may be configured to receive an input signal, process the input signal to generate a first transmit signal, and transmit the first transmit signal. The second transmitter may be configured to receive the input signal, process the input signal to generate a second transmit signal, and couple the second transmit signal into an input path of the receiver. Leakage at the receiver may thus be reduced. Some embodiments of a radio may also include a base band correction circuit and means for reducing transmitter noise that leaks into the receiver.

Abstract: A device having a sample-rate converter that may be programmed to generate samples at different rates is synchronized to an external synchronization pulse by temporarily changing the sample rate to a temporary sample rate and then changing the sample rate back to the original sample rate. Synchronization in a reduced amount of time is achieved by determining the interval between the synchronization pulse and one of the output samples and determining a processing time of the device for generating the output samples at a new rate. The system calculates a temporary sample rate based on these calculations that tends to reduce an amount of time to achieve synchronization.

Abstract: A method for calibrating an antenna array coupled to a plurality of transmitters via a plurality of couplers and a plurality of antenna element feeds is described.

Abstract: A system and method for operating a high dynamic range analog front-end receiver for long range LIDAR with a transimpedance amplifier (TIA) include a clipping circuit to prevent saturation of the TIA. The output of the clipping circuit is connected via a diode or transistor to the input of the TIA and regulated such that the input voltage of the TIA remains close to or is only slightly above the saturation threshold voltage of the TIA. The regulation of the input voltage of the TIA can be improved by connecting a limiting resistor in series with the diode or transistor. A second clipping circuit capable of dissipating higher input currents and thus higher voltages may be connected in parallel with the first clipping circuit. A resistive element may be placed between the first and second clipping circuits to further limit the input current to the TIA.

Abstract: SPI frame for simultaneously entering 8 bit daisy-chain mode from 16 bit register addressable mode. Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Large latency occurs during the entry into daisy-chain mode which increases as a function of the number of linked SPI devices. A means for simultaneously instructing all connected devices to enter/enable daisy-chain mode is disclosed.

Abstract: A multiple impedance string, multiple output digital-to-analog converter (DAC) circuit that can include a shared coarse resolution DAC, two first fine resolution DACs to receive outputs of the MSB DAC, and a multiplexer to multiplex outputs of the first and second fine resolution DACs to output terminals. The multiplexer can be configured to interchange coupling of the outputs of the first and second fine resolution DACs using one or more MSBs.

Abstract: An active antenna test system comprising an active antenna unit comprising: a test signal generator arranged to generate at least a first test signal and at least one second test signal; a plurality of transmitter modules operably coupled to the test signal generator wherein the plurality of transmitter modules are arranged to simultaneously process the first test signal and at least one second test signal to produce at least one radio frequency test signal therefrom; and at least one receiver module arranged to process one or more signals falling in at least one spectral band determined to be susceptible to intermodulation distortion products caused by the at least one radio frequency test signal being generated from the first test signal and at least one second test signal; and an intermodulation determination module operably coupled to the at least one receiver module and arranged to determine a first received intermodulation performance.

Abstract: An Ethernet or other communications module can amplify and reinforce a signal received from a non-local source without requiring a transformer or other magnetic component. A semiconductor integrated difference amplifier circuit can be used to amplify and reinforce a differential mode component of the received signal, while also attenuating a common mode component of the received signal. A transmission compensation network can generate a phase-shifted version of a locally transmitted signal being placed on the same communication terminals as the received signal during full duplex communications, for cancellation of such locally transmitted signal at inputs of a local receiver circuit. This can enhance detection of the received signal generated by the non-local source.

Abstract: Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

Abstract: A digital pre-distortion system can inversely model a power amplifier of a system to linearize the transmitter. A complex baseband model for digital pre-distortion based on a narrowband signal assumption is unworkable for an ultra wide band Cable television application. Predistortion can use a true wide band model including real-valued basis terms, obtained from a real-valued signal. When raised to a power, both even and odd harmonics or both odd or even other non-linear terms are represented and negative frequency fold-over can be accounted for. A Hilbert transform can be applied. Compressed sensing can be used to reduce the number of basis terms in the true real wide band model to generate a sparse model. Sparse equalization can be added to improve the stability of the digital pre-distortion system.

Abstract: An impedance matching circuit is provided for use with a piezotransducer that includes a parasitic capacitor comprising: an inductor coupled in parallel with the parasitic capacitor; a peak and valley detection circuit configured to detect output voltage waveform peaks and valleys; a first switch circuit configured to bias flip the output voltage waveform at a selectable first time relative to a detected peak and at a selectable first time relative to a detected valley; a second switch circuit configured to couple the inductor to the energy storage circuit at a selectable second time following each output voltage bias flip; an energy monitoring circuit to provide an indication of energy flow from the inductor to the energy storage circuit following each output voltage bias flip; and a maximum power point tracking (MPPT) circuit configured to select the first time and the second time based at least in part upon the indicated energy flow.

Abstract: A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

Abstract: A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.