Abstract: In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO and a calibration voltage generation circuit that can generate a calibration voltage for controlling a tuning voltage input of the VCO when the VCO is being coarsely tuned. Additionally, the calibration voltage generation circuit can sense a temperature of the PLL, and can control a voltage level of the calibration voltage to provide compensation based on the sensed temperature. The calibration voltage generation circuit can include a bandgap reference circuit configured to generate a zero-to-absolute-temperature (ZTAT) current and a proportional-to-absolute temperature (PTAT) current, and the calibration voltage can be generated based in part on a difference between the PTAT current and the ZTAT current.

Abstract: In an example detection system for vehicles or other objects of interest, objects are detected in real-time at full VGA 30 frame per second resolution. A preprocessor may perform run-length encoding (RLE) to provide detected edges. The image may then be scanned from the bottom up to identify vertical clusters or “stacks” or RLEs. Vertical clusters with low vertical density may be eliminated as poor vehicle candidates. Vertical clusters not eliminated may then be processed with a histogram of gradients algorithm, and confirmed with a support vector machine algorithm. A range to the nearest object may also be calculated, and a warning provided if the object is too close.

Abstract: A delta-sigma modulator is configured to sense and convert an electromagnetic field into a digital signal. An exemplary delta-sigma modulator includes a sensor component, such as an LC resonator, that is configured to sense the electromagnetic field and generate an input analog signal, where the delta-sigma modulator is configured to convert the input analog signal to the digital signal. Delta-sigma modulator can include an analog-to-digital converter coupled to the sensor component that receives and converts the input analog signal to the digital signal. Delta-sigma modulator can further include a digital-to-analog converter (DAC) coupled to the resonator and the ADC, the DAC configured to receive the digital signal from the ADC and generate a feedback analog signal.

Abstract: In an example, there is disclosed a digital to analog converter (DAC) architecture that in a first aspect provides first and second parallel paths through the DAC so as to allow a separation of a coarse and fine aspect of the DAC transfer function is described. In another aspect a DAC architecture is provided that comprises at an output of the DAC an interpolator arranged to extend the resolution of the overall DAC architecture by interpolating within the voltage range of the DAC stages that precede the interpolator. Such an interpolator can be used with both an amplifier and/or comparator to provide one or more of a buffering of the output and/or a comparison of the DAC output with signals from other circuit elements. Features of the first and second aspects may be used independently of one another.

Abstract: A compensation capacitor can be added to an amplifier for stability. Disclosed are systems and methods for improving the power supply rejection ratio (PSRR) performance of an amplifier in the presence of one or more compensation capacitors.

Abstract: A system for receiving at least two data streams and providing a single input data stream to a MIPI's CSI Tx is disclosed. The two received data streams are written into respective data buffers. The system includes a control logic configured to control reading of data stored in the buffers to a multiplexer, the read-side clock being a multiple of a frequency of a fixed frequency clock. The control logic is further configured to control the multiplexer to combine data read from each buffer that corresponds to a complete unit of data into a separate portion and multiplex the separate portions into the input data stream. In this manner, two data streams may be transmitted using a single CSI Tx. When the two data streams are received by the system from an APIX interface, the system provides a bridge between the APIX interface and MIPI's CSI Tx.

Abstract: For small cells, transceivers demand high performance while maintaining system efficiency. The present disclosure describes a highly integrated cellular transceiver that offers such features by providing one or more digital functions on-chip, onto the same die in the cellular transceiver. Effectively, the scope and boundary of the cellular transceiver is expanded to move beyond the data converters of the transceiver to include a variety of digital functions, thus integrating more of the signal chain in the cellular transceiver. Integration can greatly reduce complexity for the baseband processing, lower the cost of the overall transceiver system, reduce power consumption, and at the same time, benefit from improvements on the digital functions through integration.

Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Abstract: An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.

Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.

Abstract: A device to detect an electrical signal is provided. The device includes sensing, output, and pull-down nodes. The device includes a pull-down circuit having a native metal-oxide-semiconductor field-effect transistor (MOSFET) to pull down the output node to approximately a voltage of the pull-down node. The device includes a switch circuit having a junction field-effect transistor (JFET). The JFET turns on the pull-down circuit in response to a voltage of the sensing node being less than a first threshold. The JFET also turns off the pull-down circuit in response to the voltage of the sensing node being greater than the first threshold.

Abstract: The present invention relates to power conversion apparatus (40) configured to receive a high voltage alternating current (AC) signal at an input (42, 44) and to provide in dependence thereon a low voltage direct current (DC) signal from an output stage (58, 60). The power conversion apparatus (40) comprises a main path comprising a high voltage capacitor (46) in series with the input. The power conversion apparatus (40) also comprises a first path operative to carry current carried by the main path in at least one of a positive going part and a negative going part of the high voltage alternating current signal and a second path operative to carry current carried by the main path in a positive going part and a negative going part of the high voltage alternating current signal. The power conversion apparatus further comprises first and second switches (52, 54) which are operative to determine when a respective one of the first and second paths carries current.

Abstract: In at least one example embodiment, a microprocessor circuit is provided that includes a microprocessor core coupled to a data memory via a data memory bus comprising a predetermined integer number of data wires (J); the single-ported data memory configured for storage of vector input elements of an N element vector in a predetermined vector element order and storage of matrix input elements of an M×N matrix comprising M columns of matrix input elements and N rows of matrix input elements; a vector matrix product accelerator comprising a datapath configured for multiplying the N element vector and the matrix to compute an M element result vector, the vector matrix product accelerator comprising: an input/output port interfacing the data memory bus to the vector matrix product accelerator; a plurality of vector input registers for storage respective input vector elements received through the input/output port.

Abstract: Aspects of this disclosure relate to compensating for a relatively large offset in a signal generated by a sensor, such as a pressure sensor and/or a resistive bridge based sensor. Such offset compensation can include applying an offset correction signal generated by a configurable voltage reference, such as a voltage mode digital-to-analog converter (DAC), to an input of an amplifier included in an instrumentation amplifier to compensate for the offset of the signal generated by the sensor.

Abstract: Aspects of this disclosure relate to protecting a circuit, such as an amplifier, from transient overdrive events and/or average overdrive events. In one embodiment, an indication of average power, such as root mean squared (RMS) power of a radio frequency (RF) signal, can be compared to a first threshold and an indication of a peak RF power can be compared to a second threshold. When the indication of average power exceeds the first threshold, an average overdrive event can be detected. When the indication of peak power exceeds the second threshold, a peak overdrive event can be detected. If either a transient overdrive event or an average overdrive event is detected, a circuit, such as an amplifier, can be protected.

Abstract: A magnetic direction sensor, comprising a first array of magneto-resistive elements, said array having a first array primary direction and wherein some but not all of the magneto-resistive elements are wholly or partially provided at a first angle to the primary direction, and the remaining elements are also inclined with respect to the primary direction.

Abstract: Apparatus and methods for radio frequency (RF) switches are provided herein. In certain implementations, an RF switching circuit includes an adaptive switch bias circuit that controls gate and/or channel voltages of one or more field effect transistor (FET) switches. Additionally, the adaptive switch bias circuit is powered by a power high supply voltage and a power low supply voltage, and can be used to selectively turn on or off the FET switches based on a state of one or more switch enable signals. The adaptive switch bias circuit adaptively biases that gate and/or channel voltages of the FET switches based on a voltage difference between the power high and power low supply voltages to provide switch biasing suitable for use with two or more different power supply voltage levels.

Abstract: A low-cost system comprising a pattern arranged to encode information and a decoder for decoding the information encoded in the pattern is described. In particular, the mechanism employs a capacitive sensing technique. Electrodes are arranged (or stimulated, during operation) to each generate an electric field, and sense disturbances on the electric field caused by the pattern when the pattern is positioned over the electrodes. The spatial arrangement of the pattern allows information to be encoded on a strip or surface and decoded by capacitive sensors arranged to detect disturbances caused by possible patterns. The resulting solution is cheaper and less complex than optical solutions, e.g., barcodes and optical barcode readers. The mechanism may be used in a glucose meter for encoding and decoding an identifier for distinguishing batches of glucose meter test strips.

Abstract: The present application relates in one aspect to a method of controlling diaphragm excursion of an electrodynamic loudspeaker. The method comprises dividing the audio input signal into at least a low-frequency band signal and a high-frequency band signal by a band-splitting network and applying the low-frequency band signal to a diaphragm excursion estimator. The instantaneous diaphragm excursion is determined based on the low-frequency band signal. The determined instantaneous diaphragm excursion is compared with an excursion limit criterion. The low-frequency band signal is limited based on a result of the comparison between the instantaneous diaphragm excursion and the excursion limit criterion to produce a limited low-frequency band signal which is combined with the high-frequency band signal to produce an excursion limited audio signal.