Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).

Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage, without having to generate the reference voltage, by using charge redistribution. The switched-capacitor circuit prevents the need to dissipate power while producing the reference voltage. The switched-capacitor circuit is coupled to a comparator and to a logic circuit which provides control signals for switching. The switched-capacitor circuit comprises a plurality of capacitors arranged according to several embodiments.

Abstract: A method is disclosed for decoding a coded input stream and producing a decoded output stream. The method includes the steps of assigning each successive code in the input stream a dictionary definition that references a location in an output stream, and providing literal codes and reference codes to an output memory such that the reference codes include a source address in the output stream and a length of a code at the source address.

Abstract: A dual-mode delta-sigma analog to digital converter system is disclosed that uses a feed forward modulator and includes a low frequency resonator circuit and a high frequency resonator circuit and includes a feed-forward path from the final integrator in the high-frequency resonator circuit to a summer. The digital converter system includes a selection unit for permitting the high frequency resonator circuit and the low frequency resonator circuit to be employed in a first mode of operation. The system also permits the high frequency resonator circuit and the feed-forward path from the final integrator in the high-frequency resonator circuit to the summer to be disabled in a second mode of operation.

Abstract: A three-dimensional integrated capacitance structure comprises at least two arrays of “unit cells” on respective layers of an IC, with each unit cell comprising a center conductor and a conducting ring which surrounds the center conductor. Each array comprises a plurality of unit cells, tiled on a given IC layer at a predetermined pitch. The arrays are arranged vertically such that adjacent vertical arrays are offset in the x and y dimensions by a predetermined fraction—preferably ½—of the unit cells' pitch. The structure includes vias arranged to interconnect the arrays such that each center conductor is connected to a conducting ring of the array immediately above and/or below the center conductor, and such that each conducting ring is connected to a center conductor of the array immediately above and/or below the conducting ring.

Abstract: A current mirror circuit includes a current input node for receiving an input current, an upper, cascoded current mirror, a lower current mirror, and a biasing means. In a FET implementation, the upper mirror includes first and second cascoded FETs which are connected together at the current input node, and third and fourth cascoded FETs connected to mirror the current conducted by the first and second FETs. The lower current mirror receives the mirrored current and mirrors it back to the upper mirror, thereby providing positive feedback. The net loop gain is between zero and one. When so arranged, the third and fourth FETs conduct a current which is proportional to an applied input current. The upper mirror transistors are biased such that the voltage at the current input node is substantially closer to the supply voltage than the voltages at the gates of the first and third FETs.

Abstract: Methods and apparatus are provided for encoding data.

Abstract: A chopper-stabilized current mirror includes a pair of FETs connected to mirror an input current Iin. In one embodiment, switching networks S1 and S2 have their respective inputs connected to the FETs' drains, and are operated with clock signals CLK1 and CLK2, respectively. An ro boost amplifier A1 has its inputs connected to the outputs of S2 and its outputs connected to the gates of a pair of cascode FETs via a switching network S3 which is operated with clock signal CLK2S, with the drain of one cascode FET connected to Iin and the drain of the other providing the mirror's output Iout. S1 is clocked to reduce mismatch errors and S2 and S3 are clocked to reduce errors due to A1's offset voltage, with CLK2 and CLK2S shifted with respect to CLK1 to reduce errors due to parasitic capacitances.

Abstract: A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and other modules which may require one of the plurality of clock signals for operation. The digital baseband processor also includes a power management circuit which may power down the system oscillator when modules such as the digital signal processor and microcontroller do not require clock signals derived from the system oscillator. The power management circuit may gate off clock signals to modules when those modules do not require clock signals, without powering down the system oscillator.

Abstract: A semiconductor substrate (1) comprises first and second silicon wafers (2,3) directly bonded together with interfacial oxide and interfacial stresses minimised along a bond interface (5), which is defined by bond faces (7) of the first and second wafers (2,3). Interfacial oxide is minimised by selecting the first and second wafers (2,3) to be of relatively low oxygen content, well below the limit of solid solubility of oxygen in the wafers. In order to minimise interfacial stresses, the first and second wafers are selected to have respective different crystal plane orientations. The bond faces (7) of the first and second wafers (2,3) are polished and cleaned, and are subsequently dried in a nitrogen atmosphere. Immediately upon being dried, the bond faces (7) of the first and second wafers (2,3) are abutted together and the wafers (2,3) are subjected to a preliminary anneal at a temperature of at least 400° C. for a time period of a few hours.

Abstract: Structures and methods are provided for generating a digital display signal from an analog signal that is limited to 2N discrete analog levels and from a synchronization signal that defines spatial order for the digital display signal. These structures and methods accurately synchronize digitizers to the analog signal and they follow from a recognition that enhanced digitizer resolution will generate code patterns which easily distinguish between correct and incorrect sampling of the analog signals. Accordingly, the digitizers quantize the analog samples into an M-bit digital display signal wherein M exceeds N.

Abstract: In one embodiment, a trace buffer circuit for use with a pipelined digital signal processor (DSP) may include a series of interconnected registers that operate as a first-in first-out (FIFO) register on a write operation and a last-in first-out (LIFO) register on a read operation. On the write operation, a branch target/source address pair may be written to a first pair of trace buffer registers and, the contents of each register may be shifted two registers downstream. On the read operation, one instruction address may be read from a top register, and the contents of each register may be shifted one register upstream. The trace buffer may also include structure to enable compression of hardware and software loops in the program flow. A valid bit may be assigned to each instruction address in the trace buffer and a valid bit buffer with a structure parallel to that of the trace buffer may be provided to track the valid bits.

Abstract: Plural sum of absolute difference devices are used to calculate distortions between specified parts of specified images in a video stream. The video can be from a video camera, or other device.

Abstract: A flip around amplifier circuit is provided that includes an amplifier having first and second amplification stages, a Miller capacitor, and a resistive element in series with the Miller capacitor, where an output line of the second amplification stage can be coupled to an output line of the first amplification stage through the Miller capacitor and the series resistive element. The circuit can include a feedback capacitor having a first plate coupled to an input line of the amplifier, and a flip around switch that can be operated so as to connect an output line of the amplifier to a second plate of the feedback capacitor. The circuit's classical transfer function can include a zero associated with the Miller capacitor and the series resistive element, and a pole associated with the feedback capacitor and the on-resistance of the flip around switch, where the zero is substantially equal to the pole.

Abstract: A method of synchronizing a pulsed drive signal applied to a DC fan motor to the TACH output of the motor is described. DC motors include a rotor that rotates in a path defined by a plurality of magnetic poles and the method defines an ideal TACH output for a specific rotation speed of the rotor of the DC fan and changes the period of the drive signal if the monitored TACH output does not match the ideal TACH output such that the period of the drive signal matches the time taken for the fan to rotate through one magnetic pole of the fan.

Abstract: A single chip integrated circuit measuring circuit (1) for determining a characteristic of the impedance of an external complex impedance circuit (2) for facilitating characterization of the impedance of the complex impedance circuit (2) comprises a signal generating circuit (7) for generating a variable frequency stimulus signal for applying to the complex impedance circuit (2). A first receiving circuit (10) receives a response signal from the complex impedance circuit (2) in response to the stimulus signal and conditions the response signal. A first analog-to-digital converter (68) converts the conditioned response signal to a first digital output signal, which is read from the first analog-to-digital converter (68) through a first digital output port (14). The response signal from the complex impedance circuit (2) is a current signal, and a current to voltage converter circuit (64) converts the response signal to a voltage signal.

Abstract: An adaptive control system is described. The system includes a control having a plurality of control parameters, the control parameters providing for control of an associated plant. The control parameters are tuned using a prediction error filter, the prediction error filter selecting values of the control parameters that minimise the values of a prediction error between actual and predicted values of an autoregressive process.

Abstract: An improved coarse frequency detector includes a first storage device responsive to a data signal and a sub-multiple of a clock signal for detecting a first transition in the data signal during a predetermined state of the sub-multiple of the clock signal and generating an intermediate signal, and a second storage device responsive to the data signal and the intermediate signal for detecting a second transition in the data signal having the same polarity as the first transition during the predetermined state of the sub-multiple of the clock signal and generating an up-pulse.

Abstract: Various aspects of an integrated circuit having a DRAM are disclosed. In one embodiment an integrated circuit includes a DRAM that (1) pre-charges the bit lines to a voltage that is biased toward a weaker one of two memory cell logic states, (2) selectively stores data in an inverted form that reduces the power needed to refresh such data (in at least one embodiment), (3) retains data in the sense/latch circuits and use such circuits as a form of cache to reduce the frequency that memory cells are accessed and thereby reduce memory access time, and (4) supplies a reference (e.g., VPP) from a circuit that employs an alternate, lower power, operating mode (e.g., if the DRAM is in standby).

Abstract: An anemometer circuit comprises a sensor having a resistance which varies with temperature, immersed within a moving medium, the mass flow rate of which is to be determined. A control loop causes a current to flow through the sensor resistance, and varies the current as needed to maintain the sensor temperature at a desired value; the current is proportional to the medium's mass flow rate. In a preferred embodiment, a controller measures the sensor's voltage and current and the ambient temperature of the medium, and varies the current such that the sensor dissipates the power required to maintain its temperature at the desired value. The control loop can be arranged to maintain the sensor at a constant temperature, or at a constant differential temperature with respect to the medium's ambient temperature.