Patents Assigned to Analog Devices, Inc.
  • Patent number: 7120781
    Abstract: A register file architecture in a general purpose digital signal processor (DSP) supports alignment independent SIMD (Single Instruction/Multiple Data) operations. The register file architecture includes a register pair and an alignment multiplexer. Two 32 bit grouped words may be loaded into the register pair. Each grouped word includes four 8 bit operands. The alignment state of the 32 bit words may be determined by the two least significant bits (LSBs) of the pointer addresses of the grouped words. These LSBs are used to control the alignment MUX to select n operands from the two 32 bit grouped words and output an aligned 32 bit grouped word to execution units for parallel processing.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: October 10, 2006
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Ravi Kolagotla, David B. Witt, Bradley C. Aldrich
  • Patent number: 7119584
    Abstract: The invention recognizes that sampler linearity is degraded because transfer voltage across a sampler's buffer varies with amplitude of the analog signal being sampled. Because this transfer voltage is in the signal path it modulates the signal and distorts the resulting sample. In the invention, sampler embodiments are provided which include replica current generators that provide and route sample currents to sample capacitors so that an associated buffer transistor can transfer a faithful copy of the analog signal's potential to the sample capacitor and thereby significantly enhance the sampler's linearity. The replica current generators generally include a replica load that mimics the sample load driven by the buffer transistor.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: October 10, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Ahmed Mohamed Abdelatty Ali
  • Publication number: 20060214700
    Abstract: Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.
    Type: Application
    Filed: March 23, 2005
    Publication date: September 28, 2006
    Applicant: Analog Devices, Inc., a corporation organized and existing under the laws of the State of MA
    Inventor: David Nairn
  • Patent number: 7114093
    Abstract: A high-speed programmable serial port having a finite state machine, a clock generator capable of controlling shifting of bits from a shift register and a shift register having a bit counter capable of maintaining a numbered count of data bits in a serial output. The clock generator and shift register reduce the burdens on a finite state machine, thus improving data throughput and the ability to provided data according to a multitude of data protocols.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: September 26, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Jean-Louis Tardieux, Joern Soerensen
  • Patent number: 7112948
    Abstract: A voltage source includes first and second pn junctions which conduct the outputs of respective current sources to establish respective base-emitter voltages Vbe1 and Vbe2 at respective nodes; Vbe1 and Vbe2 can each be generated with a current I or a current N*I. An amplifier A1 has its non-inverting input connected to the second node and its inverting input connected to the first node through an input capacitor; a feedback capacitor is connected between the inverting input and a third node. Switches are connected between A1's inverting input and A1's output, between the third node and A1's output, and between the third node and a circuit common point. A control circuit operates the switches and current sources during first and second operating phases to selectively produce a temperature independent output voltage or a temperature dependent output voltage.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: September 26, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Michael P. Daly, Evaldo M. Miranda, David Thomson, A. Paul Brokaw
  • Patent number: 7113116
    Abstract: An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: September 26, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Robert J. Brewer, Colin G. Lyden, Michael C. W. Coln
  • Publication number: 20060208937
    Abstract: An analog to digital converter comprising at least two analog to digital conversion engines and a controller for controlling the operation of the analog to digital conversion engines such that during a first phase of an analog to digital conversion process the engines collaborate such that a plurality of bits can be determined during a single trial step; and during a second phase of the analog to digital conversion the conversion engines work independently; and the controller receives the outputs of at least one of the conversion engines and processes them to provide an output word.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 21, 2006
    Applicant: Analog Devices, Inc.
    Inventors: Christopher Hurrell, Colin Price
  • Publication number: 20060208935
    Abstract: A analog to digital converter, comprising: an input for receiving an input signal to be digitised; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.
    Type: Application
    Filed: November 14, 2005
    Publication date: September 21, 2006
    Applicant: Analog Devices, Inc.
    Inventors: Christopher Hurrell, Colin Lyden
  • Patent number: 7111216
    Abstract: An integrated circuit is provided in which a scan controller for controlling a scan test is integrated within the integrated circuit and shares the same input pins as a serial programmable interface of the integrated circuit.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: September 19, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Dimitris Nalbantis
  • Patent number: 7110531
    Abstract: An isolation system with analog communication across an isolation barrier includes an isolation barrier circuit having at least one isolation element; a digital to analog circuit having an analog output connected to the isolation barrier and an input for receiving an input digital signal to be communicated across the isolation barrier; and an analog to digital circuit having an input coupled to the analog output of the isolation barrier circuit for providing a digital output signal.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: September 19, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Colm J. Prendergast, Olafur Josefsson, James Wilson, Daniel T. Boyko
  • Patent number: 7109797
    Abstract: A common-mode detector includes a first difference amplifier that is connected to compare a first input voltage with a feedback voltage to provide a first result, a second difference amplifier that is connected to compare a second input voltage with the feedback voltage to provide a second result, and a feedback amplifier that is connected to drive the feedback voltage to a level that is substantially the average of the first and second input voltages in response to receiving the first and second results.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: September 19, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Anthony E. Turvey
  • Patent number: 7111155
    Abstract: A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: September 19, 2006
    Assignee: Analog Devices, Inc.
    Inventors: William C. Anderson, John Edmondson, Jose Fridman, Marc Hoffman, Russell L. Rivin
  • Patent number: 7110303
    Abstract: An electronic memory device includes at least one memory cell, a write circuit that defines an output node and mediates a discharge associated with a write operation flowing to the output node, and a write strength selection circuit that modifies at least one characteristic of the discharge. A method for testing data retention of an electronic memory device includes providing a write circuit, storing a value in at least one memory cell of the memory device, directing a weak write operation to the at least one memory cell, and sensing the memory cell to determine if the stored value changed in response to the weak write operation.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: September 19, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Richard P. Schubert
  • Patent number: 7106805
    Abstract: A dual mode transmitter for GSM and UMTS operation is provided. The GSM and UMTS paths share an oscillator and an intermediate frequency stage. Also, with the exception of the final stage of power amplification, the transmitter is provided as an integrated device.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: September 12, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Simon Atkinson, Palle Birk, Jonathan Richard Strange
  • Patent number: 7106234
    Abstract: A DAC (1) has a switched element capacitor (7, Cr) to which charge is delivered via switches (6, S1/S2) depending on required analog voltage level (Vref1, Vref2). An output switch (S3) is closed and a ground switch (S4) is opened to deliver charge to the output according to received bi-level digital inputs (+1, ?1). The control block (2) has a memory and determines an inactive output level if there is an input digital transition from +1 to ?1 or from ?1 to +1. For the inactive level S3 is kept open and S4 is kept closed. Thus, for every clock cycle with one of these transitions there is no charge transfer and hence no thermal noise. Overall noise is therefore considerably reduced.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: September 12, 2006
    Assignees: University College Cork - National University of Ireland, Analog Devices, Inc.
    Inventors: John Oliver O'Connell, Colin Lyden
  • Patent number: 7107302
    Abstract: A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: September 12, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Jose Fridman, Marc Hoffman
  • Patent number: 7106041
    Abstract: A current mirror includes an output stage that responds to a change in mirror output voltage with a change in output stage current, and an output compensation stage that, in response to the change in output stage current, introduces an output compensation current to oppose a change in mirror output current resulting from the change in output stage current.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: September 12, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Stephen A. Cohen
  • Patent number: 7107303
    Abstract: An echo canceller includes an adaptive digital filter that generates an estimated echo signal {circumflex over (z)}[k] in response to (i) a sampled input data sequence x[k] and (ii) an error signal sequence e[k] indicative of the difference between a far end signal sequence y[k] and the estimated echo signal {circumflex over (z)}[k]. The adaptive filter includes N filter taps that each provide an associated tap output signal, wherein the adaptive digital filter generates the estimated echo signal {circumflex over (z)}[k] using the associated tap output signals from M of the N filter taps selected in response to a time delay estimate signal. The adaptive filter computes filter coefficients for each of the M number of the N filter taps using the associated tap output signals from the M number of said N filter taps.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: September 12, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Joshua Kablotsky, Fabian Lis
  • Patent number: 7106604
    Abstract: An RMS-to-DC converter system is disclosed. The system includes a variable gain amplifier having transfer function ripple that receives an input signal and provides an amplifier output signal, a detector that receives the amplifier output signal and provides a detector output signal, an error amplifier that receives the detector output signal and provides an error amplifier output signal having an AC component, and a feedback circuit coupled to the error amplifier output signal and to the variable gain amplifier for providing a feedback signal to the variable gain amplifier that includes an AC component for reducing transfer function ripple of the RMS-to-DC converter system.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: September 12, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Eamon Nash
  • Publication number: 20060197586
    Abstract: Bias networks are provided for accurate generation of biases of cascode transistor arrangements. Network embodiments generate a voltage that accurately biases the transistor of a cascode arrangement at a selected point in its saturation region and this voltage is accurately transferred to the drain of a transistor via the gate-to-source voltage drops of a pair of gate-coupled transistors.
    Type: Application
    Filed: April 4, 2005
    Publication date: September 7, 2006
    Applicant: Analog Devices, Inc.
    Inventor: Arthur Kalb