Abstract: A system and method for setting analog circuit parameters requires providing a first set of data bits which represent the parameters to be set, deriving a first set of error correction bits from the values of the data bits in accordance with a predefined algorithm which enables the detection of at least one data bit error, receiving the data bits and error correction bits, deriving a second set of error correction bits from the values of the received bits in accordance with the predefined algorithm, comparing the first and second sets of error correction bits to detect the presence of data bit errors in the received data bits, correcting the data bit errors in the received data bits, and providing the corrected received data bits to the at least one analog circuit.

Abstract: A bootstrapped switch circuit can include at least one transistor, to receive an input signal and allow the input signal to pass through as an output signal based on a control signal, and a voltage-controlled voltage source, to provide first and second voltages between a gate and a source of the at least one transistor in response to the control signal. The voltage-controlled voltage source can include a differential pair and a current source. A gate of one of the differential pair can receive the control signal and a gate of the other of the differential pair can receive a logical inverse of the control signal. The current source can provide a current to connected sources of the differential pair. The first voltage can turn on the at least one transistor and be produced in response to a first logic state of the control signal resulting in the current of the current source flowing entirely through a first one of the differential pair.

Abstract: A system for correcting duty cycle errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signals. A duty cycle error detector has inputs for a pair of amplified clock signals and an output for a duty cycle error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the duty cycle error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the duty cycle error correction signal. Also, a system for correcting cross point errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signal. A cross point error detector has inputs for a pair of amplified clock signals and an output for a cross point error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the cross point error correction signal.

Abstract: An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The memory may have stored therein a plurality of instructions that, when executed, cause a digital signal pattern to be generated on a plurality of nodes. The program sequencer may be configured to control a sequence in which the plurality of instructions are retrieved from the memory and executed. The first circuit may sequentially step through a plurality of different output states in response to a clock signal. The second circuit may identify an output event when an output state of the first circuit corresponds to an output state identified by retrieved instructions of a particular type. The event execution unit may control states of signals on the plurality of nodes in a manner specified by the retrieved instructions of the particular type in response to the second circuit identifying an output event.

Abstract: A system for converting an analog signal to a digital codeword having N bit positions that includes a dual DAC structure having a small DAC and a large DAC. At least one comparator is coupled to the small DAC and large DAC. The small DAC performs bit trials to calculate bit positions 1 to M, and the large DAC with performs bit trial calculates bit positions M+1 to N after having been set with bit decisions from the bit trials of the small DAC.

Abstract: The invention is directed to a circuit and method for equalizing digital interference. A digital interference equalizing circuit may include a signal clipping unit, receiving a digital signal and clipping the digital signal based upon a clipping function, and a dithering unit adding dither to the clipped digital signal. A digital interference equalizing circuit may also include a noise detection circuit, detecting the normal activity level in a digital signal which may then be used to scale the dither added to the digital signal.

Abstract: An embodiment of a logarithmic circuit may include a logging transistor, a guard circuit arranged to force an input current into an input terminal of the logging transistor, and a positioning circuit arranged to maintain a voltage of the logging transistor. The guard and positioning circuits may include first and second feedback loops, respectively. Another embodiment of a logarithmic circuit may include a logging transistor arranged to generate a logarithmic output in response to an input current, and a feedback loop arranged to provide adaptive compensation to the logging transistor. The feedback loop may be arranged to provide compensation in response to the magnitude of the input current. Another embodiment of a logarithmic circuit may include first and second logging transistors having collectors arranged to receive input currents, and first and second feedback amplifier arranged to drive emitters of the logging transistors.

Abstract: An integrated circuit package system having a body with a top surface, a bottom surface, and a plurality of side surfaces has a leadframe and encapsulating material that encapsulates at least a portion of the leadframe. The leadframe and encapsulating material are part of the body. The leadframe has a die paddle for supporting a die, and a plurality of leads spaced from the die paddle. The encapsulating material thus also separates the die paddle from the plurality of leads. At least a first portion of the die paddle is exposed to the top surface, while at least a second portion of the die paddle is exposed to the bottom surface.

Abstract: Microelectromechanical systems (MEMS) microphone devices and methods for packaging the same include a package housing, an interior lid, and an integrated MEMS microphone die. The package housing includes a sound port therethrough for communicating sound from outside the package housing to an interior of the package housing. The interior lid is mounted to an interior surface of the package housing to define an interior lid cavity, and includes a back volume port therethrough. The MEMS microphone die is mounted on the interior lid over the back volume port, and includes a movable membrane. The back volume port is configured to allow the interior lid cavity and the MEMS movable membrane to communicate, thereby increasing the back volume of the MEMS microphone die and enhancing the sound performance of the packaged MEMS microphone device.

Abstract: Disclosed are apparatus and methods for electronic signal conversion in which a power level of the signal is used to adjust the bias current of a converter.

Abstract: An analog amplifier includes at least one signal path. Each of the at least one signal path extends between an input and an output and includes a load device coupled to the output and a transistor coupled to the input. The analog amplifier further includes a dither current source selectively coupled to one of the at least one signal path. The dither current source is capable of supplying dither current to the load device of the selected signal path directly by bypassing the transistor of the selected signal path.

Abstract: In one embodiment, a configurable timing generator outputs at least one timing signal. The configurable timing generator comprises a first timing generator configurable to output the at least one timing signal so that the at least one timing signal is adaptable to a plurality of applications. In one embodiment, a configurable parameter storage unit comprising a parameter storage area configurable so as to store a plurality of parameters at least partially defining a desired plurality of waveform hierarchy elements, where the desired plurality of waveform hierarchy elements enable the definition of a waveform. In one embodiment, a method of constructing a waveform for a configurable timing generator, the method comprising acts of constructing a first pattern waveform, where the first pattern waveform comprises a first basic pulse, and constructing a first sequence waveform, where the first sequence waveform comprises a plurality of repetitions of the first pattern waveform.

Abstract: In various embodiments, the invention pertains to systems for acoustic beamforming that include one or more speaker membranes, such as, for example, a continuous ribbon membrane, and several independently addressable drivers. Moreover, certain embodiments relate to methods for beamforming with improved directionality.

Abstract: Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization between the upconverted clock and the reference clock. In different embodiments, different types of counters and counting circuits keep track of the number of elapsed upconverted clock cycles in order to determine the specific upconverted clock cycles with longer cycle times. In some embodiments, a signal may be sent to a delay line to change the amount of delay between upconverted clock pulses, thereby increasing or decreasing a specific upconverted clock cycle time or period. In some embodiments the specific upconverted clock cycle(s) changed in each reference clock cycle may vary, which may further improve reconciliation between the upconverted clock cycles and the corresponding reference clock cycle.

Abstract: Apparatus and methods for clock and data recovery are disclosed. In one embodiment, a clock and data recovery system includes a sampler, a deserializer, a phase detector and a frequency detector. The sampler may be configured to sample a serial data stream to produce data samples and transition samples. The deserializer may be configured to deserialize the data samples and the transition samples to produce deserialized data samples and deserialized transition samples. The deserialized data samples and the deserialized transition samples can be aligned and provided to the phase detector and the frequency detector, thereby improving phase alignment and cycle slip detection.

Abstract: Apparatus and methods for rotational frequency detection are disclosed. In one embodiment, a rotational frequency detector is configured to receive samples taken from a serial data stream and to generate a frequency up error signal or a frequency down error signal. The rotational frequency detector processes a first set of samples to generate first transition data, which may be stored in a memory. The rotational frequency detector processes a second and third set of samples to generate second and third transition data. The frequency up or frequency down error signal is generated based at least partly on the first, second or third transition data. This configuration can reduce the maximum operating frequency of the rotational frequency detector, thereby simplifying the rotational frequency detector design to a point that a conventional static digital CMOS circuit design flow can be used to design the rotational frequency detector.

Abstract: A DC to DC converter comprising an inductor, first and second electrically controllable switches and a controller, wherein the first electrically controllable switch is interposed between an input node and a first terminal of the inductor and the second electrically controllable switch extends between a second terminal of the inductor and a common node or a ground, and where a first rectifier extends between the common node or ground and the terminal of the inductor and a second rectifier connects the second terminal of the inductor to an output node, wherein the controller controls the operation of the first and second switches to perform voltage step down or step up, as appropriate, to achieve a desired output voltage and wherein a decision about when to switch the first electrically controlled switch is made as a first function of a voltage error between the output voltage and a target output voltage, and an estimate of the current flowing in the inductor.

Abstract: A system and method for safing vehicle sensors includes two safety systems, each with a primary sensor for monitoring vehicle motion and activating its corresponding safety system in response to certain vehicle motions. Each sensor may act as a safing sensor for the other in the event that activation of a safety system is indicated by the primary sensor. Each sensor may also monitor the other prior to such an event, to detect a sensor malfunction before that sensor is needed to active a safety system.

Abstract: A charge/discharge control circuit for controlling current through an input/output audio device includes a first voltage reference; a second voltage reference and a waveform generation circuit responsive to the first and second voltage references for generating a multi-stage waveform profile which is approximately an inaudible waveform for suppressing audible artifacts in the input/output device.

Abstract: A variable gain amplifier includes an attenuator having a plurality of pairs of tap points, and a plurality of pairs of gm cells, wherein each pair of gm cells is coupled to a corresponding pair of the tap points, and each pair of gm cells is constructed and arranged to operate as a multi-tanh cell.