Abstract: A system and method for mutually charging switched capacitors in a switched capacitor system includes operating first and second sets of output switches during separate phases; operating first and second sets of input switches during separate phases but after the output switches are operated; and connecting the switched capacitors together after the output switches are operated but before the input switches are operated to enable them to share charge with each other toward a common mode voltage after the output switches are operated but before the input switches are operated.

Abstract: Differential amplifiers are provided with a common-mode controller that establishes an amplifier common-mode output level while it also enhances amplifier gain and output impedance. The amplifier includes cascode transistors and the controller includes positive-feedback transistors that respond to an output side of the cascode transistors and negative-feedback transistors that respond to an input side of the cascode transistors. Gain and output impedance are increased by the positive-feedback transistors and the increase is controlled by the negative-feedback transistors. Common-mode level is established by voltages between current and control terminals of the positive-feedback transistors. The differential amplifiers are shown to be especially suited for use in switched-capacitor structures.

Abstract: A SOI-based MEMS device has a base layer, a device layer, and an insulator layer between the base layer and the device layer. The device also has a deposited layer having a portion that is spaced from the device layer. The device layer is between the insulator layer and the deposited layer.

Abstract: Time-interleaved signal converter systems are provided that multiplex respective digital sequences of system converters into an interleaved digital sequence before filtering each respective digital sequence with digital filters that apply respective filter coefficients to thereby reduce system degradation caused by converter timing skews. Use of the interleaved digital sequence in the filtering process substantially increases the system bandwidth from approximately one half of the converter sample rate RC to approximately one half of a greater system sample rate RS. Converter system embodiments are preferably configured to reduce large timing skews prior to filtering the interleaved digital sequence to obtain further reduction. This combined approach has been found to enhance interleaved system performance.

Abstract: Canceling images in a quadrature modulator includes frequency shifting the baseband signal and images; filtering the frequency shifted baseband signal and images; phase and frequency shifting the baseband signal and images; filtering the phase and frequency shifted baseband signal and images; combining the filtered frequency shifted baseband signal and images with the filtered phase and frequency shifted baseband signal and images to suppress the negative frequency images and isolate the modulated baseband signal.

Abstract: A switched capacitor integrator system includes an input cascoded amplifier circuit; a summing junction; an integrating switched capacitor circuit connected to the output of the input cascoded amplifier circuit and to the summing junction; the integrating switched capacitor circuit including an input switched capacitor circuit responsive to an input and connected to the summing junction; and a correlated double sampling capacitor circuit including an offset capacitor interconnected between the summing junction and the input of the input cascoded amplifier circuit.

Abstract: An open drain driver (7) selectively switches a MOSFET switch (MN1) which is passively held in the conducting state into the non-conducting state. The MOSFET switch (MN1) switches an AC analogue input signal on a main input terminal (3) to a main output terminal (4) and the gate of the MOSFET switch (MN1) is AC coupled by a capacitor (C1) to the drain thereof. The open drain driver (7) comprises a first MOSFET (MN2) and a second MOSFET (MN3) through which the gate of the MOSFET switch (MN1) is pulled to ground (Vss). The gate of the first MOSFET (MN2) is coupled to the supply voltage (VDD) for maintaining the first MOSFET (MN2) in the open state. A control signal is applied to the gate of the second MOSFET (MN3) for selectively operating the open drain driver (7) in the conducting state for operating the MOSFET switch (MN1) in the non-conducting state.

Abstract: Micromachined structures, such as fixed drive or sensing fingers of an inertial sensor, are anchored to a substrate using multiple anchors or elongated anchors in order to reduce the bending or twisting of the micromachined structure about the anchor point.

Abstract: A motion detector capable of sensing motion of an object includes a motion sensor secured to one of a plurality of surfaces of a fastener. The fastener is directly coupleable with the object.

Abstract: A programmable read only memory includes a matrix of semi-fusible link memory cells, each including a semi-fusible link having an intact impedance and a blown impedance; a bit line voltage supply switching circuit for applying a current to at least one selected bit line; a word line address decoder for selecting a word line; and a program control logic circuit for blowing the semi-fusible links in the memory cells identified by the intersection of the selected word and bit lines; a method is disclosed of testing programmed and unprogrammed read only memory.

Abstract: An accurate, low noise conditionally resetting integrator circuit in an analog to digital system samples, with an analog to digital converter, the output of an integrating circuit a number of times during a measuring period; isolates the input for the integrating circuit during sample event; generates a reset signal in response to the integrating circuit output reaching a predetermined level; and resets the feedback capacitor of the integrating circuit by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.

Abstract: The present invention provides an improved Digital to Analog Converter (DAC) of the switched dual string DAC type, which saves on chip surface area, reduces the number of resistors and implementation cost, reduces the self capacitance and the device leakage currents of the circuit elements. The invention provides a guaranteed monotonic DAC architecture, which comprises a switching network for creating three states at a DAC transition node. In one embodiment the invention provides an unloaded state wherein a LSB DAC is de-coupled from a MSB DAC wherein the node between neighboring MSB DAC resistors is coupled to the DAC output. One of the advantages of creating the unloaded state is that the number of LSB DAC resistors is reduced as is normally the case in the prior art for a similar application.

Abstract: In one embodiment, a configurable timing generator outputs at least one timing signal. The configurable timing generator comprises a first timing generator configurable to output the at least one timing signal so that the at least one timing signal is adaptable to a plurality of applications. In one embodiment, a configurable parameter storage unit comprising a parameter storage area configurable so as to store a plurality of parameters at least partially defining a desired plurality of waveform hierarchy elements, where the desired plurality of waveform hierarchy elements enable the definition of a waveform. In one embodiment, a method of constructing a waveform for a configurable timing generator, the method comprising acts of constructing a first pattern waveform, where the first pattern waveform comprises a first basic pulse, and constructing a first sequence waveform, where the first sequence waveform comprises a plurality of repetitions of the first pattern waveform.

Abstract: An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction buffer in a pipeline stage n, an aligned instruction buffer in a pipeline stage n+1, instruction fetch logic for loading instructions into the current instruction buffer from an instruction cache or from the next instruction buffer and for loading instructions into the next instruction buffer from the instruction cache or from the instruction queue, and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer.

Abstract: An apparatus for characterising an analog to digital converter, comprising a signal generator for supplying an input signal having a first sinusoidal component to an analog to digital converter and an acquisition device for receiving and storing a plurality of output values from the analog to digital converter, and a data processor arranged to examine the output values in order to determine discrepancies due to bit weight errors and to calculate estimates of the bit weights or bit weight errors.

Abstract: A rail-to-rail amplifier suitable for use in a line-inversion LCD grayscale reference generator comprises a p-type differential pair and a first switchable current source which supplies tail current to the p-type pair in response to a first control signal, and an n-type pair and a second switchable current source which supplies tail current to the n-type pair in response to a second control signal; when its tail current is present, each pair provides a differential output current which varies with a differential input signal. A control circuit provides the control signals such that the first switchable current source is enabled when a voltage applied to the amplifier's input is closer to the amplifier's negative supply rail, and the second switchable current source is enabled when the applied voltage is closer to the amplifier's positive supply rail, such that only one input pair is active at any given time.

Abstract: A new clock driver is described for the use in the phase detector of a clock and data recovery circuit (CDR). By building a resonant LC tank, whose center frequency is similar to the clock frequency, a low power clock driver is realized. A method based upon minimizing power consumption is described for determining the value of the programmable capacitance. A programmable capacitance adjusts the center frequency of the tank so it matches the frequency of the clock and a finite state machine at startup determines the value of this programmable capacitance. A criterion for tuning the center frequency of the tank is to choose the capacitance which leads to the lowest power consumption. A low Q tank affords a reasonable compromise between power efficiency and performance in the CDR circuit.

Abstract: A correlated double sampling pixel gain amplifier includes an operational amplifier, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal. The feedback capacitor may include a capacitor array.

Abstract: A method for forming an isolation filled trench (25) in a silicon layer (21) of an SOI structure (20). The trench (25) is relieved adjacent its open mouth (30) in order to displace the commencement of bridging of the trench (25) with the filling material, to a level (36) well below a first surface (27) of the silicon layer (21) for in turn displacing voids (35) from the open mouth (30) into the trench (25) below the level (36). The trench may be relieved by forming tapered portions (40) in the side wells (29) adjacent the open mouth (30), and/or by relieving one or more lining layers (32) in the trench (25) adjacent the open mouth (30) to form tapered portion (52) and (53). Instead of relieving the trench (25) by tapering the side walls (29) relieving recesses may be formed into the first surface (27) of the silicon layer (21) adjacent the open mouth (30).

Abstract: In one implementation, a programmable processor is adapted to include a first set of registers and a second set of registers. The first set of registers may have a future file, and the second set of registers may be architectural registers. Following a termination of an instruction in the processor, the future file may be restored with values in the second set of registers. The future file is restored over more than one clock cycle.