Abstract: A digital waveform synthesiser (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesiser (10) which produces a synthesised output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A single wire bus communication system comprises a bus wire, a host device, and at least one client device, with each host and client device having pull-up and pull-down transistors to pull the bus wire “high” or “low”, respectively. The system is arranged such that, in response to a “trigger event” that requires responses from multiple client devices simultaneously, the host device enables its pull-down transistor, and each client device disables its pull-down transistor when conveying a “low” logic level onto the bus. To avoid bus contention, each client's pull-up transistor is arranged to conduct more current when enabled than the host's pull-down transistor. Then, one or more of the client devices' strong pull-ups will overcome the single weak pull-down on the bus, thereby enabling numerous client devices to respond to a command that requires a response from multiple clients.

Abstract: A method for calibrating the sensitivity of a micromachined differential-capacitor accelerometer without applying mechanical stimulation, such as shaking. The accelerometer is fabricated with dimensional control structures so that a dimensional relationship is set-up among operational features of the device. The method includes measuring the resonant frequency of a movable mass and measuring the change in the output signal of the accelerometer as the mass is displaced by electrostatic means. The sensitivity of the accelerometer is then calculated.

Abstract: A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.

Abstract: A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.

Abstract: An improved pipelined analog to digital converter that facilitates calibration for non-linearity errors and a method for obtaining calibration values. The analog to digital converter has a calibration mode in which the output bits for stages in the pipeline can be coupled to output pins of the device. Device pins that are used in normal operating mode to output the most significant bits of the ADC output are used in calibration mode to make available output bits of a pipeline stage being calibrated. A calibration method takes advantage of the outputs of the stages being directly observable to compute calibration values. The output bits of a pipeline stage are monitored as the analog input to the ADC is increased. A change in these bits identifies a subrange boundary. Errors are measured for values immediately above and immediately below each subrange boundary and used to compute correction factors.

Abstract: Methods and apparatus for amplifying a tuner input signal are disclosed. One embodiment of the invention is directed to a tuner amplifier system comprising a tuner amplifier input that receives a tuner amplifier input signal and a first amplifier comprising an input and an output. The input of the first amplifier is coupled to the tuner amplifier input. The system further comprises a second amplifier comprising an input and an output, the input of the second amplifier being coupled to the tuner amplifier input, and a switch adapted to couple one of the first amplifier output and the second amplifier output to an output of the tuner amplifier. Another embodiment of the invention is directed to a method of amplifying a tuner input signal. The method comprises acts of detecting a power of the tuner input signal, selecting a tuner amplifier to amplify the tuner input signal based on the power of the tuner input signal, and amplifying the tuner input signal using the selected amplifier.

Abstract: A SPDT switch includes an antenna port. A transmitter section is coupled to a transmitter port. The transmitter section includes a plurality of transistors that are coupled in series relative to each other. A receiver section is coupled to a receiver port. The receiver section includes a plurality of transistors that are coupled in series relative to each other, so that when the transmitter section transmits high power to the antenna port, the receive section is effectively off to provide isolation to the receive port. The receiver port is coupled to the receiver section using at least one external capacitor. The at least one external capacitor is used to improve the power handling capability and harmonic performance of the switch.

Abstract: A gain-phase detector differentially processes the outputs from two logarithmic amplifiers to provide ratiometric gain measurement, thereby eliminating intercept as a parameter. Hard-limited outputs from the dual amplifiers are multiplied in a logarithmic scalable phase detector core to provide a calibrated phase measurement output. In the preferred embodiment, two logarithmic amplifiers and other circuitry are co-integrated on a single substrate to provide a high degree of matching between the amplifiers, thereby canceling errors in the individual frequency responses of the individual amplifiers, extending the usable frequency response, and improving effective noise figure. Other numbers of logarithmic amplifiers can be used, and their various outputs can be added, subtracted, multiplied and combined in other manners to produce continuous products, continuous quotients, mixtures of products and quotients, etc., all of RF demodulated signals.

Abstract: A circuit and method are provided enabling the transfer of signals from a first voltage domain to a second voltage domain. The circuit comprises level shifters enabling the signal transfer, and is space-efficient and power efficient. A 3-wire serial protocol is used to enable the serial transmission of signals across the voltage domain boundary, and provides two distinct reset states.

Abstract: A method and device for self-test of a sensor. The method includes stimulating the sensor with signals that generate sensor outputs at a frequency that differs from the frequency of expected sensed parameter signals. The sensor output is filtered to remove the effects of the stimulation inputs, generating a sensed parameter signal. The unfiltered sensor output is compared to the expected output of the sensor with the stimulus input. A malfunctioning sensor may be detected by the comparison and appropriate action may then be taken.

Abstract: The present invention provides an improved reference source. The reference source has reduced sensitivity to the input offset voltage of the amplifier components in the reference circuit. This is achieved by subtracting two currents at the reference output node such that the combined offset sensitivity is less than the corresponding offset sensitivity for only one current.

Abstract: A device comprises a termination impedance circuit, coupled to a communication link. The termination impedance circuit provides a termination impedance of the device, wherein the impedance is selectable. A second device comprises an echo-cancel hybrid circuit, coupled to a communication link, that provides an echo cancel characteristic, wherein the characteristic is selectable.

Abstract: An amplifier has an input terminal to receive an input signal. The amplifier includes a first gain stage comprising a pair of input transistors and a second gain stage to drive an output stage. The output stage provides inverting and non-inverting differential output signals on inverting and non-inverting output nodes. The amplifier may also include a feedback signal electrically connected between the inverting and non-inverting output nodes to emitters of the input transistors through a resistor network.

Abstract: A microelectromechanical system is fabricated from a substrate having a handle layer, a silicon sacrificial layer and a device layer. A micromechanical structure is etched in the device layer and the underlying silicon sacrificial layer is etched away to release the micromechanical structure for movement. One particular micromechanical structure described is a micromirror.

Abstract: A comparator includes a circuit which provides a plurality of common-mode difference signals in response to differential input signals. The circuit provides a common-mode feedback signal in response to the plurality of common-mode difference signals. The common-mode feedback signal is used to drive the common-mode level of an amplifier to a desired value.

Abstract: A modified pipeline architecture allows the simple implementation of a foreground calibration technique with the continuous calibration benefits of the background calibration techniques. To calibrate a stage in the pipeline, a calibration voltage is presented to the input instead of the output from the previous stage. To prevent loss of information, the output data of the previous stage is passed on to a stage further down.

Abstract: An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

Abstract: In one aspect, a method and apparatus for advancing a state of a cyclic redundancy check (CRC) computation on a transmitted message via a look-up table (LUT) storing a plurality of entries associated with possible states of the CRC computation is provided. A plurality of indexes is computed based on a message chunk and a current state of the CRC computation to obtain a plurality of entries from an LUT. The plurality of entries is used to determine an advanced state of the CRC computation. In another aspect, the LUT is accessed with the plurality of indexes in parallel. In another aspect the LUT includes fewer than 2k entries, where k is the number of states advanced on each iteration.

Abstract: The invention provides a sensor element formed in a first substrate and at least one optical element formed in a second substrate, the first and second substrates being configured relative to one another such that the second substrate forms a cap over the at least one sensor element, the at least one optical element being configured to guide incident radiation on the cap to the at least one sensor element.