Patents Assigned to Analog Devices, Inc.
  • Decode and dispatch of multi-issue and multiple width instructions
    Patent number: 7069420
    Abstract: In one particular embodiment, a processor receives and processes a plurality of instruction from a single instruction register. The processor loads the plurality of instructions into a single register and determines the number and size of instructions while the instructions are in the register. Each of the plurality of instructions is then simultaneously presented to the decoder. The decoder then decodes a first of the plurality of instructions and determines whether any additional instructions are present.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: June 27, 2006
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Gregory A. Overkamp, Charles P. Roth, Ravi P. Singh
  • Integrated digital calibration circuit and digital to analog converter (DAC)
    Patent number: 7068193
    Abstract: An integrated digital calibration circuit and digital to analog converter includes a digital to analog converter (DAC) and a digital calibration circuit including a memory for storing predetermined end point coefficients of the digital to analog converter transfer function; and an arithmetic logic unit for applying the end point coefficients to the DAC input signal to adjust the end points of the DAC and/or analog signal chain.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: June 27, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Dennis A. Dempsey, Thomas G. O'Dwyer, Oliver J. Brennan, Alan Walsh, Tudor Vinereanu
  • Cache memory data replacement strategy
    Patent number: 7069388
    Abstract: A method for caching specified data in an n-way set associative memory with a copy-back update policy consists of the following steps. First, a row of the associative memory, organized as a plurality of rows and having n ways per row, is selected according to the main memory address of the specified data. The main memory provides primary storage for the data being cached. If one of the ways of the selected row holds invalid data, the specified data is cached in the way holding the invalid data and the data caching process is discontinued. If all n ways of the selected row hold valid data, the following steps are performed. First, a replacement strategy is used to select a way from the selected row. If the way selected in accordance with the replacement strategy holds unmodified data, the specified data is cached in the way selected by the replacement strategy and the data caching process is discontinued.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: June 27, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Zvi Greenfield, Dina Treves, Gil Zukerman
  • Integrated circuit package device
    Patent number: 7064442
    Abstract: The invention relates to integrated circuit package devices including at least two component chips. In particular the invention describes such devices having a transformer provided between the two components chips, the transformer providing isolation between the component chips and wherein the total assembly is sufficiently small that it can be integrated in standard IC packages.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: June 20, 2006
    Assignee: Analog Devices, Inc.
    Inventors: William A. Lane, Mike A. O'Neill, John R. Reidy, Tom D. Moore, Nicola M. O'Byrne, Leo P. McHugh
  • Hardware loops and pipeline system using advanced generation of loop parameters
    Patent number: 7065636
    Abstract: In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: June 20, 2006
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Ryo Inoue, Ravi P. Singh, Charles P. Roth, Gregory A. Overkamp
  • Method for efficiently computing a fast fourier transform
    Patent number: 7062523
    Abstract: A method for computing an out of place FFT in which each stage of the FFT has an identical signal flow geometry. In each stage of the presently disclosed FFT method the group loop has been eliminated, the twiddle factor data is stored in bit-reversed manner, and the output data values are stored with a unity stride.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: June 13, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Marc Hoffman, Jose Fridman
  • Impedance network with minimum contact impedance
    Patent number: 7057491
    Abstract: An impedance network configuration in the form of a snake-like or ladder structure is provided. The ladder configuration enables the provision of tabs extending outwardly from the normal conducting path, the tabs providing a location for the provision of contact layers. Using such a configuration the contribution of the contact impedance can be minimized and also programming of the configuration may be effected.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: June 6, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Dennis A. Dempsey
  • 3G radio
    Patent number: 7058364
    Abstract: A radio transceiver suitable for use in a mobile telephone is provided. The transceiver is operable in dual modes so as to be able to operate with both GSM and UMTS systems. In a preferred embodiment the transmitter section receives base band signals and up-converts them to an intermediate frequency of approximately 450 MHz. This is then mixed with local oscillator frequency of approximately 1.35 GHz, such that a difference frequency allows operation in the GSM 850/950 MHz band, and the sum frequency allows operation in the GSM 1800/1900 MHz bands. The frequency addition allows operation in the UMTS band. The receiver portion of the transceiver comprises a direct conversion receiver for down-converting the received signal without use of an intermediate frequency.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: June 6, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Simon Atkinson, Palle Birk
  • Enhanced processing methods for wireless base stations
    Publication number: 20060114936
    Abstract: A method for use in a wireless communication system includes performing at least part of physical layer processing in one or more digital signal processors of a selected type, and performing at least part of medium access control processing in the same one or more digital signal processors. The physical layer processing may include coding, spreading and modulation. The medium access control layer processing may include placing data units in queues according to priority and scheduling data units for transmission or retransmission.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 1, 2006
    Applicant: Analog Devices, Inc.
    Inventor: Matthijs Paffen
  • Single wire digital interface
    Patent number: 7053667
    Abstract: A single-wire digital interface for receiving digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having “first” and “second” pulse widths, respectively. A low-pass filter produces an output that increases at a known rate for the duration of a received data pulse, and a comparator produces an output that toggles when the filter output exceeds a predetermined threshold. A clock edge is generated when a received pulse terminates; the clock and comparator outputs are provided to a latch circuit. The interface latches a ‘1’ when the received pulse's width is equal to the “first” pulse width, and latches a ‘0’ when the received pulse's width is equal to the “second” pulse width. Data is preferably preceded by a “start-of-packet” (SOP) bit pattern and followed with a “end-of-packet” (EOP) bit pattern.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: May 30, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Andrew T. K. Tang
  • Phase-error reduction methods and controllers for time-interleaved analog-to-digital systems
    Patent number: 7053804
    Abstract: Methods and controllers are provided to estimate and reduce phase errors between converters of time-interleaved analog-to-digital systems by generating corresponding error signals in the form of difference signals. The difference signals concern differences between magnitudes of first adjacent samples and interleaved second adjacent samples of the converters. The difference signals can be applied (e.g., to a converter's input sampler or to a variable delay element inserted after the converter) to substantially reduce the phase errors. The methods and controllers may be economically implemented because they can be realized with simple operations (e.g., addition and subtraction). Although some embodiments are facilitated with knowledge of parameters of the analog input signal, others do not require this knowledge so long as the signal is restricted to lie within a single Nyquist zone.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: May 30, 2006
    Assignee: Analog Devices, Inc.
    Inventor: David G. Nairn
  • Apparatus and method for generating a code mask
    Patent number: 7053800
    Abstract: A new output mask for a m-sequence generator is produced by modulo-2 summing a number of intermediate masks. The intermediate masks are produced by shifting a shift template by amounts corresponding to offsets of set bits in an existing output mask. If an intermediate mask contains set bits beyond its portion corresponding to the new output mask, then they are wrapped back.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: May 30, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Timothy Fisher-Jeffes
  • Apparatus and method for controlling the state variable of an integrator stage in a modulator
    Patent number: 7053807
    Abstract: An apparatus for controlling the state variable of an integrator stage in a modulator including a detector circuit for generating an overload signal when the modulator is overdriven, a control circuit responsive to the overload signal for generating switching control signals during the overdriven condition, and an integrating capacitance circuit having an unswitched portion and a switched portion and responsive to the switching signals for repeatedly connecting the switched portion between the unswitched portion and a discharge path to receive and drain charge when the modulator is overdriven to increase the lossiness of the integrator stage and control a state variable of the modulator.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: May 30, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Eric Gaalaas
  • Frequency assisted digital timing recovery
    Patent number: 7050521
    Abstract: A method and system is provided for acquisition of the initial timing for a digital phase lock loop timing recovery system. A modified loop filter and post filter allows for an instantaneously change the oscillation frequency of a controllable oscillator and an instantaneous relative change of the sampling phase of the sampled data. These two features are used for initial timing recovery, in which the process of frequency and phase acquisition is separated into two independent steps. Once the initial timing is acquired, the timing recovery system is operated as a conventional digital phase lock loop timing recovery system to track additional frequency and phase drifts at the receiver with respect to the transmitter.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: May 23, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Reza Alavi
  • Apparatus and method for adding multiple-bit binary-strings
    Patent number: 7051062
    Abstract: Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of the first output, the second adder being operable to add a plurality of m-bit addends, m being smaller than or equal to n. The apparatus further comprising at least two electronic-circuits, operatively associated with the first adder and the second adder. The first adder, the second adder and the at least two electronic-circuits are constructed and designed to obtain the value, the overflow status and a sign of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: May 23, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Michel Jalfon
  • Differential stage voltage offset trim circuitry
    Patent number: 7049889
    Abstract: Differential stage voltage offset trim circuitry involves the use of one or more trim circuits, each of which is dedicated to trimming one particular source of voltage offset (Vos) error for a “main” differential pair. One trim circuit may be dedicated to trimming Vos error that arises due to mismatch between the main pairs' threshold voltages, and another trim circuit may be dedicated to trimming Vos error that arises due to mismatch between the main pairs' beta values. Another trim circuit can trim Vos error due to gamma mismatch between the main pair transistors, and respective trim circuits can be employed to trim Vos error that arises due to threshold mismatch and/or beta mismatch between the transistors of an active load driven by the main pair. Several trim circuits may be employed simultaneously to reduce offset errors that arise from each of several sources.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: May 23, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Arthur J. Kalb
  • Method for automatic thermal calibration of a cooling system
    Patent number: 7047756
    Abstract: This disclosure describes a method for operating a cooling device in a thermal system that is responsive to an operating parameter and dynamically changes the operating parameter to achieve a maximum operating temperature for any system regardless of the subsystem variation.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: May 23, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Robin Laurie Getz, David Edward Hanrahan
  • Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period
    Patent number: 7050919
    Abstract: A method for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period includes measuring delay spacing between the plurality of clock signal edges, calculating programmed delay spacing, calculating ideal signal edges from the programmed delay spacing and adjusting the clock signal edges to match the respective ideal signal edges. A plurality of calibrated clock signal edges is produced that are selectively available to a user.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: May 23, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Kenneth Stern
  • Galois field polynomial multiplication
    Publication number: 20060106910
    Abstract: In one aspect, a multiplier for performing multiplication of a first operand and a second operand is provided. The multiplier comprises a matrix having a plurality of matrix elements arranged in a plurality of columns, a first plurality of storage elements to store at least a portion of the first operand, the first plurality of storage elements connected diagonally to the matrix, and a second plurality of storage elements to store at least a portion of the second operand, the second plurality of storage elements connected vertically to the matrix. In another aspect, a multiplier for computing at least a partial product of a first operand having a first length and a second operand having a second length is provided.
    Type: Application
    Filed: November 16, 2004
    Publication date: May 18, 2006
    Applicant: Analog Devices, Inc.
    Inventor: Wei An
  • DAC having switchable current sources and resistor string
    Patent number: 7046182
    Abstract: A DAC architecture is provided which is monotonic in operation despite any mismatches in the components. The architecture is a segmented architecture and hence it is area efficient. This is achieved by effecting a generation of analog voltages by driving current sources to resistors in response to digital input. In a preferred embodiment, the invention provides a resistor string coupled between output and vref-, and set of current sources. The current sources are switched to nodes between resistors to generate voltages at the output.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: May 16, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Kaushal Kumar Ja, Arindam Raychaudhuri, Michael T. Tuthill, William Hunt, David A. Phelan, Colin G. Lyden