Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.

Abstract: A processing system includes a processing circuit having one or more buses, a memory interface unit to control access by the processing circuit to a memory, and a metrics module. The metrics module includes one or more metrics registers and a metrics controller to monitor one or more operations selected from memory interface unit operations and bus operations, and to store metrics information corresponding to the monitored operations in the metrics registers. The monitored operations can include memory access operations, arbitration operations, bus operations, and the like. The metrics information can be analyzed to provide a basis for improving performance of a program that is executed on the processing system.

Abstract: The invention is directed to a circuit and method for equalizing digital interference. A digital interference equalizing circuit may include a signal clipping unit, receiving a digital signal and clipping the digital signal based upon a clipping function, and a dithering unit adding dither to the clipped digital signal. A digital interference equalizing circuit may also include a noise detection circuit, detecting the normal activity level in a digital signal which may then be used to scale the dither added to the digital signal.

Abstract: A flexible engine for implementing digital signal processing (DSP) functions involving repeating various arithmetic/logical operations on a stream of data includes multiple programmable filter elements, at least one of which includes a microcode control program for internal control of the programmable filter element. The engine also includes programmable interconnection logic coupled to the programmable filter elements for selectively combining, scaling, and accumulating output values from the first plurality of programmable filter elements and selectively providing accumulated values as inputs to the first plurality of programmable filter elements. A filter controller coupled to the programmable filter elements and the programmable interconnection logic includes its own microcode control program for external control of the programmable filter elements and the programmable interconnection logic. Multiple engines can be combined to form larger, more powerful engines.

Abstract: A method and device for measuring active power of AC with respect to a fundamental frequency or harmonic frequencies using a DPLL include generating via the DPLL a pair of substantially mutually orthogonal sinusoid signals in response to an input voltage data signal, mixing a first sinusoid signal of the pair with a current data signal of the alternating current via a first low-pass filter, mixing the first sinusoid signal of the pair with a voltage signal of the alternating current via a second low-pass filter, and computing an active power of the alternating current based on a further mixing of an output from the first low-pass filter and an output from the second low-pass filter.

Abstract: A system and method for measuring reactive power which uses a pair of quadrate carriers to add a 90 degree phase shift to a voltage path or a current path in a power meter. The quadrate carriers have the same frequency but are offset in phase from each other by 90 degrees.

Abstract: The invention provides a method of processing a sequence of operands to produce compiled code for a target data processor, the method comprising the steps of: automatically analysing a source code to produce a fist representation of that code in single static assignment form; transforming the first representation into a second representation by unlooping ? nodes within the single static assignment form so as to create code suitable for tree pattern matching to be performed thereon; performing tree pattern matching on the second representation of the code; and re-looping the ? nodes.

Abstract: The invention provides a sensor element formed in a first substrate and having a thermal barrier disposed between the sensor element and a heat source provided elsewhere on the first substrate. The thermal barrier includes at least one pair of trenches formed within the first substrate, individual trenches of the pair being separated by a cavity.

Abstract: A transceiver for use in a bidirectional optical communication link over a multimode channel is provided. The transceiver includes a single transverse mode light source in a transmitter. A waveguide or fiber based bidirectional coupler projects the transmitter mode to the high modes of the multimode channel. A detector coupled to predominantly all the modes of the channel via the waveguide or fiber based bidirectional coupler.

Abstract: A differential two-stage Miller compensated amplifier system with capacitive level shifting includes a first stage differential transconductance amplifier including first and second output nodes and an output common mode voltage, a second stage differential transconductance amplifier including non-inverting and inverting inputs and outputs and an input common mode voltage, and a level shifting capacitor circuit coupled between the first and second output nodes and the non-inverting and inverting inputs for level shifting between the output common mode voltage of the first stage and the input common mode voltage of the second stage.

Abstract: A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the IC design that do not meet metal density requirements are then identified. The identified one or more regions are then filled with one or more filler metal polygons as a function of the metal density requirement and coupling capacitance between metal lines.

Abstract: In one aspect, an apparatus for data conversion is provided.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: A Galois field linear transformer trellis system includes a Galois field linear transformer matrix; an input selection circuit for providing to the matrix a number of input bits in one or more trellis bit streams and a trellis state output of the matrix and a programmable storage device for configuring the matrix to perform a multi-cycle Galois field transform of the one or more trellis bit steams and trellis state output to provide a plurality of trellis output channel symbols and a new trellis state output in a single cycle.

Abstract: In accordance with one embodiment of the invention, a packaged microchip has 1) a base with a mounting surface having a given electrical interconnector, and 2) a microchip with a plurality of side surfaces, a top surface, a bottom surface, and a given electrical pad on at least one of the top and bottom surfaces. The packaged microchip also has 3) a given solder ball secured to one of the top and bottom surfaces of the microchip. The given solder ball also is connected to the given electrical interconnector to electrically connect the given electrical pad and the given electrical interconnector. At least one side surface of the microchip is generally parallel with the mounting surface of the base.

Abstract: A vertical mount pre-molded type package for use with a MEMS sensor may be formed with a low moisture permeable molding material that surrounds a portion of the leadframes and forms a cavity in which one or multiple dies may be held. The package includes structures to reduce package vibration, reduce die stress, increase vertical mount stability, and improve solder joint reliability. The vertical mount package includes a first leadframe having first leads and molding material substantially surrounding at least a portion of the first leads. The molding material forms a cavity for holding the MEMS sensor and forms a package mounting plane for mounting the package on a base. The cavity has a die mounting plane that is substantially non-parallel to the package mounting plane. The first leads are configured to provide electrical contacts within the cavity and to provide electrical contacts to the base.

Abstract: A system and method for calibrating an RDAC to obtain an expected resistance are disclosed. In one embodiment, a method of obtaining an expected resistance from an RDAC circuit includes receiving a digital signal comprising a digital code by an on-chip calibration code engine, automatically deriving a calibrated digital code based on resistance versus digital code characteristic curves of an expected RDAC and the RDAC associated with the calibration code engine, and inputting the calibrated digital code into the RDAC associated with the calibration code engine to obtain an expected resistance. The method also includes forming the resistance versus digital code characteristic curves of the expected RDAC and the RDAC, computing a gain error and an offset error using the formed resistance versus digital code characteristic curves of the RDAC and the expected RDAC and storing the gain error and the offset error in a non-volatile/volatile RDAC memory.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: A redundant cross point switching is achieved by mapping a redundant column/row of point cells and enabling at least one of the switching devices which is associated with each column/row to define an alternate path around the defective point cell which replicates the function of the switching location of the defective point cell.

Abstract: A testing system contactor with an integral temperature measurement sensor.