Abstract: Pipelined converter systems include a plurality of converter stages in which some stages generate and pass a residue signal to a succeeding stage for further conversion. The generation of the residue signal can inject spurious charges into a reference source that is used in the generation. The spurious charges reduce the accuracy of the residue signal and the accuracy of the system. Residue generator embodiments are thereby formed to provide reduction charges to the reference source that are arranged to oppose and reduce the spurious charges. This reduction of spurious charges significantly enhances system accuracy and linearity.

Abstract: A method of estimating a change of a variable over a measurement window, including the steps of taking multiple samples of the variable during the measurement window, defining a weight to be associated with each sample, the weight varying as a function of position of the sample within the measurement window, processing the samples taking account of their weight to form an estimate of the change in the variable.

Abstract: One or more micromachined (MEMS) switches switch attenuators, such as resistors, into or out of a signal path, such as of a test instrument. The MEMS switches can be fabricated on the same substrate as the attenuators, or the switches or attenuators can be mounted on the same substrate as the others are fabricated. An instrument probe includes attenuators and MEMS switches that are controlled by the instrument and/or by a control circuit in the probe. Optionally, the probe includes reactive elements, such as capacitors, and MEMS switches to compensate for electrical characteristics of the probe and/or probe lead, and the probe or a test instrument automatically sets the MEMS switches to connect appropriate ones of the reactive elements to a signal path within the probe.

Abstract: An SAR analog-to-digital converter performs bit decisions in each of a plurality of clock cycles A sense circuit monitors signals input to a latch within a comparator of the ADC and, when the signals are sufficient to establish a bit decision, the sense circuit terminates a currently active clock cycle causes a bit decision to occur in advance of a normal expiration of the clock cycle. If the signals are insufficient to establish a bit decision prior to a default expiration time of the clock cycle, the clock cycle concludes at the default expiration time.

Abstract: Disclosed are apparatus and methods for electronic signal conversion in which a power level of the signal is used to adjust the bias current of a converter.

Abstract: A side-ported MEMS microphone package defines an acoustic path from a side of the package substrate to a microphone die disposed within a chamber defined by the substrate and a lid attached to the substrate. Optionally or alternatively, a circuit board, to which the microphone package is mounted, may define an acoustic path from an edge of the circuit board to a location under the microphone package, adjacent a bottom port on the microphone package. In either case, the acoustic path may be a hollow passage through at least a portion of the substrate or the circuit board. The passage may be defined by holes, channels, notches, etc. defined in each of several layers of a laminated substrate or circuit board, or the passage may be defined by holes drilled, molded or otherwise formed in a solid or laminated substrate or circuit board.

Abstract: Embodiments of the present invention provide an apparatus and control method for an analog front end (AFE) amplifier for controlling DC restore operations. According to the exemplary method, a first input stage of the AFE is controlled to operate as a continuous time amplifier that has high input impedance and draws substantially no input leakage current for a first predetermined area of an imaging sensor image array. The first input stage is controlled to operate as a sample and hold amplifier with DC restore functionality for a second predetermined area of the imaging sensor image array. According to an embodiment, the AFE input stage operates as a continuous time amplifier when reading pixels from the sensor's active image array but operates as a sample and hold amplifier with DC restore when reading pixels from the image array that correspond to so-called ‘black-level’ pixels or pixels that otherwise fall outside the sensor's active image field.

Abstract: Accelerating processing of a non-sequential instruction stream on a processor with multiple compute units by broadcasting to a plurality of compute units a generic instruction stream derived from a sequence of instructions; the generic instruction stream including an index section and a compute section; applying the index section to localized data stored in each compute unit to select one of a plurality of stored local parameter sets; and applying in each compute unit the selected set of parameters to the local data according to the compute section to produce each compute unit's localized solution to the generic instruction.

Abstract: An integrated energy metering system having an energy meter including a voltage ADC for sensing voltage, a current ADC for sensing current, a microcontroller; a first memory device for storing program data for the energy meter; and a plurality of circuit blocks; a voltage monitor for monitoring a primary power supply; a power supply switch circuit for selectively applying one of the primary and auxiliary power supplies to the energy meter; and a system controller responsive to the voltage monitor for operating the switch circuit to apply the auxiliary power supply when the primary power supply voltage decreases below a predetermined level and gating the power to a first class of circuit blocks in the energy meter and applying power continuously to a second class of circuit blocks.

Abstract: An amplifier front-end comprises an input node for receiving a common-mode voltage Vcm, a differential transistor pair having first and second inputs and outputs, a capacitor, a reference voltage Vref, an error correction circuit, and a switching network. The switching network charges the capacitor to Vref; couples the capacitor to the differential pair's first input and couples Vref to the pair's second input such that the voltage at both inputs is ˜Vref; and couples the input node to the capacitor's other terminal such that the voltage at the first input is level-shifted to ˜(Vcm+Vref). The error correction circuit—typically an auto-zero circuit—is coupled to the differential pair's outputs and arranged to reduce charge injection error and kT/C noise components that would otherwise be present in the outputs due to the level shift.

Abstract: A multi-branch frequency translation system converts a plurality of independent input clocks to a common frequency. One of the converted clock signals is selected as a dominant clock. The remaining converted clock signals are edge-synchronized with the dominant clock. When the system selects another converted clock signal for use as the dominant clock, the newly selected signal already is edge-synchronized with the dominant clock and, therefore, switchover losses can be avoided. The dominant clock can be subject of further frequency translation processes and output from the system.

Abstract: A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks—an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit.

Abstract: A phase locked loop (PLL) based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The PLL is configured as an all digital PLL and includes a bang-bang phase frequency detector, digital loop filter, and digitally-controlled oscillator. The frequency translator is located in either the reference clock path for division or the PLL feedback loop path for multiplication. The SDM produces a predictable noise characteristic set with known stochastic properties which can be used to smooth any discontinuity in the bang-bang phase frequency detector. The predictable noise of the SDM will produce a dithering delay that eliminates any hard discontinuities. This allows for a bang-bang phase frequency detector based digital PLL.

Abstract: A thin film resistor (5) of an integrated circuit comprises an elongate resistive film (7) extending between electrical contact pads (10,11). A low impedance element (20) overlays and is electrically coupled to a portion of the resistive film (7) in an intermediate portion (22) thereof adjacent a second side edge (17) of the resistive film (7) for conducting current in parallel with the intermediate portion (22), and for reducing current density in the intermediate portion (22). First and second transverse edges (28,29) formed by spaced apart first and second slots (26,27) which extend from a first side edge (16) into the resistive film (7) define with a first side edge (16) of the resistive film (7) and the low impedance element (20) first and second trimmable areas (30,31) in the intermediate portion (22).

Abstract: The invention provides a sensor array having a plurality of sensor elements formed in a first substrate and having a plurality of die temperature sensors located thereabout. Each of the die temperature sensors are configured to provide an output related to the temperature of the die on which they are located, the sensor elements providing an output indicative of the intensity of radiation incident thereon.

Abstract: AC-coupled equivalent series resistance (ESR) is introduced into a control circuit to provide additional stability in the feedback control loop. A sub-circuit emulates the effect of a higher value ESR in the output capacitor. The additional ESR in the feedback control loop inserts a zero into the transfer function that describes the circuit response at a desired frequency. The added zero compensates for the effects of unwanted or unavoidable poles in the transfer function, allowing for a greater range of input signal frequencies.

Abstract: A method and system for determining camera positioning information from an accelerometer mounted on a camera. The accelerometer measures the orientation of the camera with respect to gravity. Orientation measurement allows user interface information to be displayed in a “right side up” orientation on a viewfinder for any camera orientation. Alternatively, an artificial horizon indicator may be displayed in the viewfinder. The accelerometer may also measure camera movement. Camera movement information together with camera orientation can be used to determine camera usage. Additionally, camera movement information can be used to determine a minimum shutter speed for a sharp picture.

Abstract: Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal.

Abstract: A logic signal isolator including a micro-transformer with a primary winding and a secondary winding. A transmitter circuit drives the primary winding in response to a received input logic signal such that, in response to a first type of edge in the logic signal, at least a first amplitude signal is supplied to the primary winding and, in response to a second type of edge in the logic signal, a second different amplitude signal is supplied to the primary winding. A receiver circuit receives corresponding first amplitude and second amplitude signals from the secondary winding and reconstructs the received logic input signal from the received signals.

Abstract: A method of operating a circuit for processing a digital signal is disclosed. The circuit includes various circuit stages having respective enabled states. A present signal path is established which includes circuit stages in their respective enabled states. Power is disabled to selected circuit stages not used in the present signal path so as to minimize power consumption in the disabled circuit stages. A data signal is then processed through the circuit stages in the present signal path. Before a next signal path is needed, power is re-enabled to selected disabled circuit stages in the next signal path to allow the enabled circuit stages to approach their respective enabled states. Then the next signal path can be established including the enabled circuit stages in their respective enabled states. The data signal can then be processed through the circuit stages in the next signal path.