Abstract: Described is a system and method for centralized synchronization for the transportation of data between devices in different clock domains. In a preferred embodiment, synchronization logic synchronizes read data from an asynchronous peripheral to a bus clock. Rather than being located on each peripheral, the synchronization logic is located in the bus interface logic. When there is an indication that synchronization is needed for a peripheral, the synchronization logic samples the data bus twice or more and compares the values of consecutive data samples. If the data samples are equal, this data is returned to the bus master. If they are different, the data in the next cycle is returned to the bus master.

Abstract: A property of a magnetic sensor, deployed on a micro machined optical element and exposed to a magnetic field, changes as the position of the micro machined optical element changes with respect to a magnetic field or, alternatively, when the magnetic field changes with respect to the micro machined optical element. The electrical, optical and/or mechanical change in sensor property varies according to the position, and a measurement of the property change tracks the change in orientation of a moveable portion of the optical element.

Abstract: Images are obtained for image compression. The images are compared using sum of absolute difference devices, which have arithmetic parts, and accumulators. The sign bits of the accumulators are determined at a time of minimum distortion between two images. These sign bits are associated with sets of probabilistically-similar parts. When other sets from that set are obtained later, an early exit is established.

Abstract: A method and circuit for measuring the optical modulation amplitude in the operating region of a laser diode is described. The method utilises two measurements of OMA, each measurement being related to the slope in a specific portion of the operating region of the power/current characteristic curve of the laser diode. By combining the two measurement values, the invention provides a 1 measurement for OMA in the operating region of the laser diode that allows for the presence of a non-linear response in the region.

Abstract: A bandgap voltage reference is described which has reduced sensitivity to noise and amplifier offset. By configuring the circuitry such that the base width of the component transistors is not varied on application of a bias, it is possible to obviate the Early effect.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: A signal processing component is provided where a swapper 702 is provided upstream of real and imaginary processing elements 704 and 706 within a system for processing complex signals. A further swapper 710 is provided downstream of the elements 704 and 706. The swappers 702 and 710 operate in unison.

Abstract: A pulse width modulated common mode feedback technique for a differential charge pump includes averaging the output of a differential charge pump to determine the common mode voltage; generating from the pump up and pump down pulses a set of up source pulses and down source pulses and a set of up sink pulses and down sink pulses and adjusting, in response to a difference between a reference voltage and the common mode voltage, the width of at least one of the sets of source and sink pulses to match the reference common mode voltages.

Abstract: A signal conditioning system includes first and second converters coupled to a random clock which provides a random sampling rate. Corresponding offset sensor coupled with the first and second converters sense and adjust an offset signal difference. A gain sensor is coupled with the first and second converters to sense a gain difference between the first and second converters and a gain corrector is coupled with the gain sensor to adjust the gain difference.

Abstract: An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.

Abstract: In one embodiment, a programmable processor is adapted to include loop hardware to increase processing speed without significantly increasing power consumption. During a first pass through a loop, a first subset of a sequence of instructions may be loaded into the loop hardware. Then, during subsequent passes through the loop the first subset may be issued from the loop hardware while a second subset is retrieved from a memory device. In this manner, the second subset may be issued with no additional penalty after the first subset has been issued.

Abstract: In an embodiment, a pipelined processor includes a future file for storing updated data address values generated by a data address generator (DAG). These updated values may be provided to the DAG for subsequent address calculation operations.

Abstract: A multimode voltage regulator includes a low current pass device and a high current pass device each adapted for connection between a power supply and a load; an error amplifier responsive to a difference between a reference voltage and a function of the voltage on the load to produce an error signal; and a low power driver responsive in a low load power mode to an error signal for operating the low current pass device to provide low power to the load and a high power driver responsive in a high load power mode to an error signal for operating the high current pass device to provide high power to the load for maintaining efficiency over high and low power load operation.

Abstract: A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

Abstract: Accelerometer offset is reduced by forming mass support structures within an inner periphery of the mass, affixing the mass support structures to the substrate by at least one anchor positioned near the mass' center of mass, and affixing the sensing fingers proximate to the anchor. The mass support structures can be affixed to the substrate using a single anchor or multiple anchors that are positioned close together. The sensing fingers can be affixed to the substrate or to the mass support structures. The mass is typically suspended from within its periphery but toward its outer periphery.

Abstract: A brown-out detector that continuously monitors power supply voltage and provides an output signal that transitions to a logic HIGH state when the monitored power supply voltage exceeds a predetermined threshold value. One embodiment of the present invention comprises a first voltage reference with respect to ground that varies in direct proportion to absolute temperature, a second voltage reference with respect to the supply voltage that varies inversely with absolute temperature, and a comparator having the first voltage reference coupled to one input, and the second voltage reference coupled to the other input, such that the comparator output changes state when the power supply voltage exceeds a predetermined threshold voltage that is relatively independent of absolute temperature. The circuit may also be configured such that the first voltage reference varies inversely with absolute temperature, while the second voltage reference varies in direct proportion to absolute temperature.

Abstract: Methods and apparatus are provided for supplying data to a processor in a digital processing system. The method includes holding data required by the processor in a cache memory, supplying data from the cache memory to the processor in response to processor requests, performing a cache line fill operation in response to a chache miss, supplying data from a prefetch buffer to the cache memory in response to the cache line fill operation, and speculatively loading data from a lower level memory to the prefetch buffer in response to the cache line fill operation.

Abstract: A translinear amplifier is disclosed. A loop amplifier drives the bases of the input and output transistor pairs from the differential collector voltage of the input pair. The loop amplifier contains a third differential pair (a gain pair). The tail current of the gain pair is inversely related to the tail current of the input pair, such that loop amplifier gain remains stable when the transconductance of the input pair changes (due, e.g., to input gain changes). In one embodiment, a linear-in-dB interface is provided that adjusts input pair tail current exponentially (and gain pair tail current exponentially and inversely) to linear voltage changes at a gain input.

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: An pipeline analog-to-digital converter (ADC) is provided that is capable of applying calibration at a resolution greater than the resolution of a digital output signal provided by the ADC. The ADC includes a calibration component adapted to apply calibration bits to digital output bits generated by stages of the pipeline and corresponding to samples of an analog input signal. The ADC also includes a random number generator that provides at least one random bit having a sub-LSB bit weight. The calibration bits and the at least one random bit are applied as a dither to the digital output bits such that, on average, the digital output signal provided by the ADC is calibrated at a sub-LSB resolution.