Patents Assigned to Analog Devices, Inc.
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Patent number: 6795752Abstract: An integrated convective accelerometer device. The device includes a thermal acceleration sensor having a thermopile and a heater element; control circuitry for providing closed-loop control of the thermopile common-mode voltage; an instrumentation amplifier; clock generation circuitry; voltage reference circuitry; a temperature sensor; and, output amplifiers. The device can be operated in an absolute or ratiometric mode. Further, the device is formed in a silicon substrate using standard semiconductor processes and is packaged in a standard integrated circuit package.Type: GrantFiled: November 3, 2000Date of Patent: September 21, 2004Assignees: Memsic, Inc., Analog Devices, Inc.Inventors: Yang Zhao, Adrian Paul Brokaw, Michael E. Rebeschini, Albert M. Leung, Gregory P. Pucci, Alexander Dribinsky
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Patent number: 6789187Abstract: In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.Type: GrantFiled: December 15, 2000Date of Patent: September 7, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Ravi Kolagotla, Juan G. Revilla
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Patent number: 6789184Abstract: In an embodiment, an address pipeline corresponding to an instruction pipeline in a processor, for example, a digital signal processor (DSP), may generate and track the instruction address of each instruction at each stage. The address pipeline may include program count (PC) generation logic to automatically calculate the PC of the next instruction based on the width of the current instruction for sequential program flow. The address pipeline may also track valid bits associated with each instruction and store the address of the oldest valid instruction for return to the original program flow after a disruptive event.Type: GrantFiled: September 29, 2000Date of Patent: September 7, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Gregory A. Overkamp
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Patent number: 6788157Abstract: A programmable frequency synthesizer including a voltage-controlled oscillator, a regenerative frequency divider and a programmable integer divider, that provides wideband frequency coverage from a single narrowband oscillator. The voltage-controlled oscillator may generate a first signal having a first frequency. The regenerative frequency divider is coupled to the voltage-controlled oscillator and receives the first signal and performs a fractional multiplication of the first frequency of the first signal to provide a second signal a having a second frequency. The programmable integer divider is coupled to the regenerative frequency divider, and receives the second signal and divides the second frequency by a predetermined integer to provide a third signal having a third frequency.Type: GrantFiled: October 28, 2002Date of Patent: September 7, 2004Assignee: Analog Devices, Inc.Inventor: Robert M. Clarke
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Patent number: 6784747Abstract: An amplifier circuit and fabrication method including a bias input node, an RF input node, an RF output node, and a plurality of amplifier cells. Each cell has a plurality of discrete emitter contacts of a first conductivity type, a plurality of discrete base contacts of a second conductivity type and grouped in two or more groups, at least one collector contact of the first conductivity type connected to the RF output node, and a base capacitor for each group having two electrodes: an input electrode coupled to the RF input node and an output electrode coupled to a group of discrete base contacts. There is also a base resistor for each group having an input coupled to the bias input node and an output coupled to a group of discrete base contacts. An emitter resistor is coupled to each discrete emitter contact to provide more effective base ballasting and thermal stability than with a cascode arrangement of HBT transistors.Type: GrantFiled: March 20, 2003Date of Patent: August 31, 2004Assignee: Analog Devices, Inc.Inventors: Shuyun Zhang, Robert Jeffery McMorrow
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Patent number: 6784500Abstract: A circuit including at least one low voltage input, at least one high voltage output, and a field transistor having a source, a drain and a control region. The circuit may comprise a high-voltage amplifier. In this embodiment, an electrical connection between the high-voltage output terminal and the field transistor control region, and an electrical connection between the input terminal and a second transistor. Various embodiments of the field transistor are described.Type: GrantFiled: August 31, 2001Date of Patent: August 31, 2004Assignee: Analog Devices, Inc.Inventor: Mark Alan Lemkin
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Patent number: 6785518Abstract: A transceiver circuit is disclosed for use in radio frequency communication systems. The circuit includes a transmitter circuit, a receiver circuit and a local oscillator circuit. The local oscillator circuit includes at least one oscillator input signal having a frequency that is a non-integer multiple of the transmission frequency of the radio frequency communication system. The oscillator input signal is used to produce a transmitter local oscillator signal and a receiver local oscillator signal.Type: GrantFiled: February 15, 2002Date of Patent: August 31, 2004Assignee: Analog Devices, Inc.Inventors: Simon Atkinson, Jonathan R. Strange, Robert J. Broughton, Alexander Shvarts
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Patent number: 6781361Abstract: A power metering system including a first modulator receiving a first analog voltage associated with a current and outputting a first digitized signal. A second modulator receives a second analog voltage and outputs a second digitized signal. A first lowpass filter filters out high frequency noise associated with the first signal and decimates the frequency of the first digitized signal. The first lowpass filter outputs a first filtered signal. An interpolator performs up sampling of the signal associated with the first filtered signal. The interpolator outputs a first up sampled signal. An integrator integrates the first up sampled signal. The integrator outputs an integrated signal. A first multiplier multiplies the second digitized signal and integrated signal, and outputs a multiplied signal. The multiplied signal being used to measure power.Type: GrantFiled: April 26, 2002Date of Patent: August 24, 2004Assignee: Analog Devices, Inc.Inventor: Eric Nestler
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Patent number: 6778010Abstract: High-speed differential amplifiers are provided for use with switched-capacitor structures. These amplifiers reduce current demand during small-signal operation and generate high slew currents during large-signal operation. These processes are realized with slew-current generation structures that directly generate slew currents during large-signal operation and thus avoid the degradation of intermediate current-genration structures.Type: GrantFiled: June 18, 2003Date of Patent: August 17, 2004Assignee: Analog Devices, Inc.Inventor: Christopher Michalski
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Patent number: 6778126Abstract: Analog-to-digital converter (ADC) structures and methods are provided that reduce an initial converter nonlinearity by introducing an inverse nonlinearity into the converter's response that is substantially the inverse of the initial converter nonlinearity. In a pipelined ADC embodiment, for example, upstream converter stages are selected that generate an upstream digital code which defines sufficient upstream code words to designate respective segments of the inverse nonlinearity. In response to each of the upstream code words, the conversion gain of the remaining downstream converter stages is then sufficiently adjusted to insert the inverse nonlinearity into the converter response.Type: GrantFiled: November 21, 2002Date of Patent: August 17, 2004Assignee: Analog Devices, Inc.Inventor: Ahmed Mohamed Abdelatty Ali
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Patent number: 6778013Abstract: Buffer amplifiers are provided with a replica current generator that supplements a buffer transistor and is configured to provide a replica current which substantially equals required load currents in the amplifier's output load. Because the current of the buffer transistor remains constant, its base-emitter voltage Vbe remains constant and the amplifier linearly reproduces the input signal Sin across the output load.Type: GrantFiled: February 21, 2003Date of Patent: August 17, 2004Assignee: Analog Devices, Inc.Inventor: Ahmed Mohamed Abdelatty Ali
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Publication number: 20040156532Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.Type: ApplicationFiled: February 9, 2004Publication date: August 12, 2004Applicant: Intel Corporation and Analog Devices, Inc., a Delaware corporationInventors: Bradley C. Aldrich, Jose Fridman
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Patent number: 6774694Abstract: A timing vernier applies a pair of stable bias voltages to intermediate points of an impedance string to establish reliable and calibratable delay cell biases for a fine multiplexer. A coarse input multiplexer is switched to a new timing signal substantially immediately after passing a prior valid timing signal to maximize the time prior to each valid output that the waveform is independent of the prior delay pattern. Logic circuitry is provided for three different phase differential regimes between successive timing signals to ensure that invalid output signals separated by less than a clock period are not produced. Mask commands are inserted into a series of timing control commands to equalize the average rates of writing and reading out the timing control commands with the mask commands skipped at readout.Type: GrantFiled: December 24, 2002Date of Patent: August 10, 2004Assignee: Analog Devices, Inc.Inventors: Kenneth J. Stern, Jeff W. Barrell, Paul S. Cheung, Thomas Alan Gaiser
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Patent number: 6774723Abstract: A circuit for matching a first mirror transistor with a second mirror transistor in a current mirror includes a bias transistor and a diode connected transistor to match such mirror transistors. More particularly, the circuit is a part of an amplifier having an output with a quiescent voltage and at least one rail voltage. The first mirror transistor has a first terminal coupled to the output and a second terminal coupled to the at least one rail voltage. To effectuate its mirroring function, the bias transistor is coupled to a first terminal of the second mirror transistor, and the diode connected transistor is coupled to both a second terminal of the second mirror transistor and the at least one rail voltage. The bias transistor has a terminal with a quiescent voltage that is substantially equal to the quiescent voltage of the output.Type: GrantFiled: June 20, 2002Date of Patent: August 10, 2004Assignee: Analog Devices, Inc.Inventor: Faramarz Sabouri
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Patent number: 6774823Abstract: A method and apparatus for synchronizing actions of two circuits or two parts of one circuit where each circuit utilizes a different clock signal. More than one clock signal are derived from a master clock signal and run at the same frequency but have an unknown or variable phase difference. The invention solves the problem of coupling two clocked circuits where synchronization is required to properly read or sample a signal from a data line connecting the two circuits. An error window is defined during which sampling is suppressed, for example to avoid sampling during data transitions. The method of apparatus involves time shifting a pseudo-signal to generate two time-shifted signals and then defining the error window as the time during which the two time-shifted signals differ from one another.Type: GrantFiled: January 22, 2003Date of Patent: August 10, 2004Assignee: Analog Devices, Inc.Inventor: Bernd Schafferer
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Patent number: 6774683Abstract: A system and method are provided for controlling the on/off timing relationship between two transistors in a differential that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns one while the other is turning off. An overlap signal is derived from the tail node excursion and is indicative of whether the on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to derive the on/off signals is adjusted based on the control signal. When more overlap is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals.Type: GrantFiled: August 13, 2002Date of Patent: August 10, 2004Assignee: Analog Devices, Inc.Inventor: Bernd Schafferer
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Patent number: 6771095Abstract: A level translating digital switch in which a switching element provides switching and level translation between a first system and a second system that operate using different logic supply voltages. In a situation where the supply voltage for the first system is larger than the supply voltage for the second system, the switching element is driven by a voltage lower than the logic supply voltage of the first system.Type: GrantFiled: January 31, 2003Date of Patent: August 3, 2004Assignee: Analog Devices, Inc.Inventors: John Olan Dunlea, John P. Quill
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Patent number: 6771203Abstract: Parallel analog-to-digital converter systems are provided in which converters are temporally interleaved. In particular, converters are partitioned into at least two converter groups which are assigned different respective group converter periods that are multiples of the system periods. With converters in each of the converter groups, respective samples are processed over that group's respective group converter period and the group converter periods of all converters are temporally shifted to process each of the samples with at least one of the converters.Type: GrantFiled: April 29, 2003Date of Patent: August 3, 2004Assignee: Analog Devices, Inc.Inventor: David Graham Nairn
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Patent number: 6771271Abstract: A relatively high speed circular memory device, in combination with other processes, improves image processing efficiency. To that end, a method and apparatus of processing image data stored in an initial memory logically divides the image into a plurality of contiguous strips. A first plurality of the strips are stored in a working memory having a circular addressing arrangement, where the working memory is faster than the initial memory and has a plurality of sequential address locations. The first plurality of strips are contiguous and have a start address. In addition, the first plurality of strips are stored in the working memory in a contiguous manner, and processed through the working memory relative to the start address.Type: GrantFiled: June 13, 2002Date of Patent: August 3, 2004Assignee: Analog Devices, Inc.Inventors: Ke Ning, Marc Hoffman, Gabby Yi
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Publication number: 20040148553Abstract: An integrated circuit is provided in which a scan controller for controlling a scan test is integrated within the integrated circuit and shares the same input pins as a serial programmable interface of the integrated circuit.Type: ApplicationFiled: April 4, 2003Publication date: July 29, 2004Applicant: Analog Devices, Inc.Inventor: Dimitris Nalbantis