Abstract: Complex sound events are created by generating multiple different kinds of simpler sounds with randomly varying repetition rates. The average repetition rate can also be variable. The values of sound parameters such as wave selection, pitch distribution, pan distribution and amplitude distribution can have random distributions, as determined by various control inputs, some of which have their own random distributions.

Abstract: A novel clock control circuit completely removes the inter-symbol interference (ISI) in the DAC output waveform without any significant increase in power consumption and silicon area of the DAC. The novel circuit does not increase the requirement for slew rate and bandwidth of the amplifier.

Abstract: Methods and structures are provided for generating a digital display signal in response to an analog display signal whose amplitude varies at a pixel rate and in response to a synchronization signal that defines spatial order for the analog display signal. The structures include a transform generator for providing a Fourier transform of the digital display signal and a transform analyzer which generates frequency and phase control signals in respective response to the frequency of an error spectral component and amplitudes of image spectral components in the transform. The frequency and control signals are applied to respectively adjust the sample rate of the sample clock and alter the phase of the sample clock.

Abstract: A calibration system for a communication system is provided featuring a transmitter circuit, a receiver circuit, a transmission medium having a transfer function for transmitting a signal between the transmitter and receiver circuits, and a calibration system responsive to the altered reference signal of the transmitter circuit for adjusting the reference signal level of one of the transmitter and receiver circuits to compensate for variations in the transmission signal due to the transfer function.

Abstract: A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said seco

Abstract: An efficient approach to generating the bias resulting during the joint equalization/decoding of a Complementary-Code-Keying (CCK) based system is provided that includes a bias generator system having a plurality of inputs responsive only to feedback filter coefficients, the bias generator generating, based upon said feedback filter coefficients, a plurality of output signals corresponding to the bias of a Fast Walsh Transform system for cancelling the bias.

Abstract: Methods and apparatus for reducing the thermal noise integrated on a storage element are disclosed. One embodiment of the invention is directed to a sampling circuit comprising a sampling capacitor to store a charge, the sampling capacitor being exposed to an ambient temperature. The sampling circuit further comprises circuitry to sample the charge onto the capacitor, wherein thermal noise is also sampled onto the capacitor, and wherein the circuitry is constructed such that the power of the thermal noise sampled onto the capacitor is less than the product of the ambient temperature and Boltzmann's constant divided by a capacitance of the sampling capacitor. Another embodiment of the invention is directed to a method of controlling thermal noise sampled onto a capacitor. The method comprises an act of independently controlling the spectral density of the thermal noise and/or the bandwidth of the thermal noise.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull operation. According to some embodiments, the switched capacitor buffer displays an optimal combination of design simplicity, low power consumption and high-frequency response.

Abstract: A flip around amplifier circuit is provided that includes an amplifier having first and second amplification stages, a Miller capacitor, and a resistive element in series with the Miller capacitor, where an output line of the second amplification stage can be coupled to an output line of the first amplification stage through the Miller capacitor and the series resistive element. The circuit can include a feedback capacitor having a first plate coupled to an input line of the amplifier, and a flip around switch that can be operated so as to connect an output line of the amplifier to a second plate of the feedback capacitor. The circuit's classical transfer function can include a zero associated with the Miller capacitor and the series resistive element, and a pole associated with the feedback capacitor and the on-resistance of the flip around switch, where the zero is substantially equal to the pole.

Abstract: A method and a secure mode controller are provided for controlling context switching between secure and user modes in a processing system including a processor and a memory management unit. The method comprises monitoring the memory management unit to detect a non-cache access to an entry point address that contains a secure mode entry instruction, verifying, in response to detection of the entry point address, that the secure mode entry point instruction is executed by the processor, and enabling context switching from the user mode to the secure mode in response to verifying that the secure mode entry instruction is executed by the processor. Each cache line of an instruction cache and a data cache may have a tag containing a secure bit to identify a secure cache line or a non-secure cache line.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. Channel control logic controls transfer of data through the DMA channels in response to parameters contained in at least one DMA descriptor having a programmable format.

Abstract: A homodyne receiver is provided for receiving GSM and UMTS transmissions. The receiver may also be used for other transmission schemes. The receiver includes an electronically reconfigurable low pass filter and an off set generator for providing DC offset correction for offsets which may be generated as a result of coupling between a local radio frequency oscillator and the receiver front end.

Abstract: In a first embodiment of the invention there is provided an electronic chip for use with an automatic testing equipment device testing a device under test. The device under test has a plurality of pins and the electronic chip is placed in a channel of a test card that is associated with one of the pins. An input signal is provided to a pin of the device under test and the resulting output is provided to the pin electronics for the channel of the test card. In most embodiments, the output signal is a voltage signal. One purpose for the electronic chip is to measure jitter based upon timing measurements performed by the electronic chip. Jitter measurements are particularly important for high-speed serial devices. The electronic chip includes an integrating time measurement circuit for receiving the input signal and producing an output signal including a timing measurement of at least a portion of the input signal.

Abstract: An interpolated variable gain amplifier (VGA) utilizes multiple active feedback cells. The active feedback cells may be implemented as transconductance (gm) cells that replicate gm cells in the interpolated input stages.

Abstract: A wireless terminal circuit includes a variable high frequency clock oscillator that provides a high frequency clock signal and a fixed low frequency clock oscillator that provides a low frequency clock signal. A phase-locked loop adjusts a ratio of the frequency of the high frequency clock signal to the low frequency clock signal by adjusting the frequency of the high frequency clock signal. The phase locked loop includes a divider for dividing the high frequency clock signal, the divide ratio of which divider is controlled by a sigma-delta modulator. A wireless terminal local oscillator calibration circuit includes a frequency control circuit including both the high frequency clock oscillator and the low frequency clock oscillator.

Abstract: A multimode fiber system includes a transmitter for transmitting an optical signal and a receiver that receives the optical signal. At least one mode filter is coupled between the receiver and the transmitter and passes only a specific set of fiber modes from the transmitter to be received by the receiver. The at least one mode filter comprises a tapered core section that includes a double taper configuration joined at the narrowest regions and in which each end of the two tapers has dimensions compatible with the fiber at that end.

Abstract: A small signal amplifier with a large signal output boost stage are connected between first and second supply rails. The small signal amplifier receives first and second input signals and provides an output signal at an output node which drives a load. Under small signal conditions, the output signal varies approximately linearly with the difference voltage. However, under large signal conditions, a rail-to-rail large signal output boost stage connected to the output node is arranged to drive the output node close to the first or second supply rail as needed to provide the current demanded by the load. The large signal output boost stage is off in small signal conditions, but comes on rapidly and transfers maximum charge to the load under large signal conditions.

Abstract: A galvanically isolated signal conditioning system includes a signal conditioning circuit on an integrated circuit chip; a flying capacitor; and a galvanically isolating MEMS switching device on an integrated circuit chip for selectively switching the flying capacitor from across a pair of input terminals in one state to across the input terminals of the signal conditioning circuit in another state.

Abstract: An inertial sensor includes at least one pair of sensor elements arranged in a linear array. Each sensor element has a frame and a movable mass suspended within the frame. The frames of each pair of sensor elements may be coupled so that the frames are allowed to move in anti-phase to one another along parallel axes but are substantially prevented from moving in phase with one another.