Abstract: Apparatus and techniques described herein can include using an electronic circuit comprising a rectifier circuit, an open-circuit voltage (OCV) sampling circuit coupled to the output of the rectifier circuit, and a regulator circuit coupled to the output of the rectifier circuit. In an example, an isolation switch can be located between the regulator circuit and the rectifier circuit, the isolation switch configured to isolate the regulator circuit from the rectifier circuit for sampling of the open-circuit voltage by the open-circuit voltage sampling circuit. In another example, a buffer circuit can be used, such as placed in-line with a divider circuit between a divider circuit and an open-circuit voltage sampling capacitor. In this manner, the buffer circuit can provide a low output impedance, isolating the voltage sampling capacitor from the divider circuit.

Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.

Abstract: Apparatus and methods for current sensing in switching regulators include a current sensing circuit to sense current of a power stage of a power converter. The power converter can include first and second transistors. The current sensing circuit comprises a transistor that is a scaled version of one of the transistors of the power converter. A circuit of the current sensing circuit matches a drain-to-source voltage of the transistor of the current sensing circuit to the corresponding transistor of the power converter. A current mirror generates a current that mirrors the current flowing through the transistor of the current sensing circuit. A first resistor converts the mirrored current to a current sensed signal.

Abstract: A time-interleaved analog-to-digital converter (ADC) uses M analog-to-digital converters to sample an analog input signal to produce digital outputs. The M ADCs, operating in a time-interleaved fashion, can increase the sampling speed several times compared to the sampling speed of just one ADC. The time-interleaved ADC can be programmed and reconfigured to trade one performance metric for another. For example, more time can be given to comparator to improve bit error rate or more time can be given to an amplifier for improved settling which improves SNR, SFDR etc. If the time-interleaved converters are randomized, then the amount of ‘color’ in the noise floor shape can also be traded for other performance metrics.

Abstract: Mixers with improved linearity are disclosed. A diode or FET ring mixer is implemented with at least one parallel shunt element coupled with the ring mixer, the shunt element providing shunt to a diode or FET, for example, to reduce the effect of nonlinear or off resistance and/or capacitance. Linearity, isolation, symmetry, even order harmonics of the ring mixer, or any combination thereof can be improved as a result. The linearity of the ring mixer with parallel shunt resistors can be further improved by adding series resistors in the ring according to certain embodiments.

Abstract: Continuous-time analog-to-digital converters (ADCs) such as continuous-time delta-sigma ADCs and continuous-time pipeline ADCs, has input resistor structure at the input. The input resistor structure is typically tunable, and the tunability is usually provided by metal-oxide semiconductor field effect transistor (MOSFET) switches. Core MOSFETs, which has a terminal-to-terminal voltage <1.0V, is used for the switches for performance reasons. However, a typical implementation can have reliability issues with overloading inputs. An improved input resistor protection circuit can solve this issue by generating on and off voltages for the switches inside the tunable resistor structure based on a summing node voltage where one side of the switch is connected.

Abstract: Methods and apparatus to reduce localized transistor operating temperature increases in fully integrated voltage regulator circuits are provided. Transistor self-heating effects are reduced by dispersing heat more evenly over the integrated circuit die, via use of nested voltage regulator circuits and/or use of more than one transistor in a voltage regulator circuit pass device. An electrically parallel-connected group of multiple individual integrated transistors may be laid out across cooler areas of the integrated circuit die, such as in substantially linear sets or rings of devices near the outer die perimeter. Each transistor in the group may better disperse its own heat if it is thermally segregated from other self-heating devices, as through a minimum physical layout spacing. Transistor bias voltage mismatch tolerances, load currents, and routing resistances may interrelatedly determine the number of individual transistors needed in a group.

Abstract: Fault detection techniques for control of sensor systems. A sensor control integrated circuit (“IC”) may include a fault detection system for coupling to the sensor supply lines. The system may detect faults for each of the sensor supply lines. The fault detection system may level shift sensor supply line signals from a first voltage domain to a second voltage domain appropriate for the fault detection system of the controller IC. The fault detection system may level shift source potential voltages from the first voltage domain to the second voltage domain to detect predetermined fault types. The fault detection system may compare the second domain voltages from the sensor supply lines to voltages representing predetermined fault types and may generate fault status indicators based on the comparison.

Abstract: Wireless sensor nodes for enabling network connectivity in a wireless sensor network system are disclosed herein. An exemplary method includes receiving a Lightweight Machine-to-Machine (LWM2M) network packet from a network node over a network; using a media access control (MAC) layer to route the LWM2M network packet to a sensor node when a destination Internet Protocol (IP) address specified in the LWM2M network packet matches a virtual IP address; and using a network layer to route the LWM2M network packet to the sensor node when the destination IP address does not match a virtual IP address.

Abstract: Flexible antennas for harvesting electromagnetic energy are described. The flexible antenna may be a far field antenna and may comprise a flexible substrate, a first metal layer disposed on one side of the flexible substrate, and a second metal layer disposed on an opposite side of the flexible substrate. The first and second metal layers may be connected through one or more vias. The first metal layer may be sized to capture electromagnetic energy at a frequency in an ISM band.

Abstract: A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data.

Abstract: A method and apparatus for estimating and compensating TX LO leakage using circuitry on a loopback path connecting the transmitter and receiver are provided. The TX LO leakage may be estimated by measuring the DC signal on the receiver, measuring the phase difference between the received LO signal and the receiver LO signal, and filtering LO harmonics that may arise from the use of non-linear mixers. The DC signal on the receiver may be measured by opening and closing the loopback path, or changing the gain of the loopback path, or flipping the phase of looped back TX signal. The method may be used in an initialization or tracking calibration scheme.

Abstract: A stress shield for a plastic integrated circuit package is disclosed. A shield plate is attached by an adhesive to a top surface of an integrated circuit die such that the shield plate covers less than all of the top surface and leaves bond pads exposed. A molding material is applied over the shield plate and the integrated circuit die. The shield plate shields the integrated circuit die from stresses imparted by the molding material.

Abstract: Embodiments of the present disclosure provide code readers for reading codes provided as patterns imprinted on objects. Light interacts with a pattern by e.g. being reflected from or transmitted through the pattern, and at least some of the light that has interacted with the pattern is incident on photosensitive element(s) of one or more photodetectors of a code reader. The code reader employs centroid-measuring photodetector(s), i.e. photodetectors that detect light in such a manner that centroid of a pattern can be obtained directly from the photocurrents generated as a result of the photosensitive elements detecting light incident thereon. The code reader is then configured to process the detected light to determine a centroid of the pattern from the detected light and to decode data encoded in the pattern based on a position of the centroid. Such code readers are substantially less complex than camera-based devices and avoid mechanical scanning.

Abstract: Various embodiments efficiently detect the presence of an external capacitor electrically coupled to the output of a voltage regulator by perturbing the voltage output of the voltage regulator while the regulator is in operation and supplying, or ready to supply, regulated voltage to a load, and detecting the reaction of the regulator's output.

Abstract: Embodiments of the present disclosure are based on a recognition that some processors are configured with instructions to compute logarithms and exponents (i.e. some processors include log and exp circuits). Embodiments of the present disclosure are further based on an insight that the use of the existing log and exp circuits could be extended to compute certain other functions by using the existing log and exp circuits to transform from a Cartesian to a logarithmic domain and vice versa and performing the actual computations of the functions in the logarithmic domain, which may be computationally easier than performing the computations in the Cartesian domain.

Abstract: A hardware-locked encrypted backup (HWLE-BU) that is locked to a single hardware device using the device's unique hardware identity, based on a Physically-Unclonable Function (PUF) or other suitable means providing a unique hardware identity. The HWLE-BU is bound to a specific hardware identity such that only the physical device that created the HWLE-BU can decrypt it, i.e., restoring HWLE-BU data requires utilizing the same physical hardware device in the decryption process.

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract: In an example embodiment, a power switching circuit of an automobile audio bus (A2B) chip is provided in a bi-directional, multi-node two-wire conductor system that includes a plurality of A2B chips interconnected on a twisted wire pair bus (A2B bus), with at least one A2B chip functioning as a master and the remaining A2B chips functioning as slaves. The power switching circuit of the A2B chip powers up a next downstream A2B chip in the A2B bus sequentially according to a power switching procedure, and the power switching circuit is configured to detect faults in the A2B bus before, during, and after the power switching procedure. Each A2B chip enables power to the next downstream A2B chip without risk of damage to any components in the system due to line faults on the downstream A2B bus, or collapse of the power supply at the local A2B chip.

Abstract: Controlling the output voltage of a power supply involve determining a remote load coupled to the power supply and setting the output voltage based on the determined remote load and a predetermined maximum current for the power supply. The remote load may be measured, for example, by applying a predetermined current to the load, measuring the voltage across the load, and computing the effective load (resistance) value based on the supplied current and the measured voltage. Such measurement may be done using an analog-to-digital converter.