Abstract: Disclosed herein are envelope detectors with high input impedance, and related methods and systems. In some embodiments, an envelope detector with high input impedance may include: a swinging stage including first, second, and third transistors, wherein the third transistor and an active transistor are arranged as a differential pair, the first transistor is the active transistor when an input to the envelope detector is positive, and the second transistor is the active transistor when the input to the envelope detector is negative; and a feedback circuit, coupled to the swinging stage, to provide an output signal representative of a rectification of the input.

Abstract: A bus driver is provided that can withstand over voltages being applied to its output terminal without the protection circuit detracting from the voltage swing that can be provided by the driver. The circuit arrangement also allows transistors having good on state resistance and large tolerance of drain-to-source voltages to be used.

Abstract: Apparatus and methods are disclosed related to managing characteristics of a mobile device based upon capacitive detection of materials proximate the mobile device, a capacitive gesture system that can allow the same gestures be used in arbitrary locations within range of a mobile device. One such method includes receiving a first capacitive sensor measurement with a first capacitive sensor of the mobile device. The method further includes determining a value indicative of a material adjacent to the mobile device based on a correspondence between the first capacitive sensor measurement and stored values corresponding to different materials. The method further includes sending instructions to adjust a characteristic of the mobile device based on the determined value indicative of the material adjacent to the mobile device. In certain examples, gesture sensing can be performed using capacitive measurements from the capacitive sensors.

Abstract: A temperature sensing system can include first and second temperature sensing circuits and a digitizing encoder. The first and second temperature sensing circuits can include respective devices with semiconductor junction areas. Temperature information can be determined from one or more characteristic signals measured from the temperature sensing circuits. A feedback circuit can be configured to provide one or more offset signals to the digitizing encoder. The one or more offset signals can correspond to components or characteristics of the first and second temperature sensing circuits. In an example, at least one of the first and second temperature sensing circuits can include an adjustable load circuit for use with the other of the first and second temperature sensing circuits.

Abstract: The present application relates in one aspect to a method of controlling diaphragm excursion of an electrodynamic loudspeaker. The method comprises dividing the audio input signal into at least a low-frequency band signal and a high-frequency band signal by a band-splitting network and applying the low-frequency band signal to a diaphragm excursion estimator. The instantaneous diaphragm excursion is determined based on the low-frequency band signal. The determined instantaneous diaphragm excursion is compared with an excursion limit criterion. The low-frequency band signal is limited based on a result of the comparison between the instantaneous diaphragm excursion and the excursion limit criterion to produce a limited low-frequency band signal which is combined with the high-frequency band signal to produce an excursion limited audio signal.

Abstract: A bias current generators that may be implemented in low power environments is described. The current generator can be implemented without using resistors and may be used to generate reference currents and voltages. It may also be used to generate voltage references where the output of the circuit is to at least a first order temperature independent.

Abstract: Systems and methods disclosed herein provide for enhancing the low frequency (DC) gain of an operational amplifier with multiple correlated level shifting capacitors. In an embodiment, the operational amplifier is level shifted with a first correlated level shifting capacitor in a first phase and, then, is level shifted again with at least a second correlated level shifting capacitor in at least a second, non-overlapping, consecutive phase. In an embodiment, the multiple correlated level capacitors are controlled by a switching circuit network.

Abstract: An active voltage divider circuit is provided comprising: a first node; a second node; a third node; multiple FET load devices coupled in series between the first node and the second node; multiple first switches, each associated with a different FET load device and configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device; and second switch circuitry configured to selectably couple a drain of a FET load device, from among the multiple FET load devices, to the third node.

Abstract: A comparator circuit's signal range can be enhanced using an input signal attenuation circuit. In an example, a comparator circuit receives an input signal and a reference signal. The input signal can be conditioned by one or both of the attenuation circuit and a conditioning circuit, and a resulting conditioned signal can be presented to a compare element. Under first operating conditions where the input signal is approximately equal to the reference signal, the attenuation circuit can be substantially bypassed and a first resulting conditioned signal can be presented to the compare element. Under second operating conditions where the input signal is substantially greater than the reference signal, the attenuation circuit receives a portion of the input signal and a different second resulting conditioned signal can be presented to the compare element.

Abstract: Embodiments of the present disclosure provide mechanisms that enable designing an FIR filter that would have a guaranteed globally optimal magnitude response in terms of the minimax optimality criterion given a desired weight on the error in the stopband versus the passband. Design of such a filter is based on a theorem (“characterization theorem”) that provides an approach for characterizing the global minimax optimality of a given FIR filter h[n], n=0, 1, . . . , N, where optimality is evaluated with respect to a magnitude response of this filter, |H(ej?)|, as compared to the desired filter response, D(?), which is unity in the passband and zero in the stopband. The characterization theorem enables characterizing optimality for both real-valued and complex-valued filter coefficients, and does not require any symmetry in the coefficients, thus being applicable to all non-linear phase FIR filters.

Abstract: Embodiments of the present disclosure are based on a recognition that some processors are configured with instructions to compute logarithms and exponents (i.e. some processors include log and exp circuits). Embodiments of the present disclosure are further based on an insight that the use of the existing log and exp circuits could be extended to compute certain other functions by using the existing log and exp circuits to transform from a Cartesian to a logarithmic domain and vice versa and performing the actual computations of the functions in the logarithmic domain, which may be computationally easier than performing the computations in the Cartesian domain.

Abstract: In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

Abstract: An authenticatable device according to one embodiment includes a reconfigurable physical unclonable function (‘RPUF’) used with one parameter to recover sensitive values (e.g., a secret or a share of a secret) and a different parameter to encode and store values (e.g., challenge-helper pairs) correlated to the sensitive values. In another embodiment, a pair of RPUFs is used instead of a single PUF, with one RPUF used to recover sensitive values and the other RPUF used to encode and store correlated values. In still another embodiment, the desired expiration of values can be enforced by employing redundant RPUFs; when the device is powered on, one (or more than one, but less than all) of the RPUFs is selected and transitioned to a new configuration, invalidating any correlated values previously constructed using the old configuration, and the RPUF that was not reconfigured is used to recover the sensitive value(s) using the remaining correlated value(s).

Abstract: An inverter based on a compound semiconductor uses a depletion mode transistor as the pull-up device, and a current source to bias the pull-up device. The current source is electrically coupled to a source terminal of the pull-up device. As a result, the current source continues to conduct current through the pull-up device, whether the inverter output is high or low, to ensure rapid response of the inverter.

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

Abstract: A successive approximation routine (SAR) analog-to-digital converter integrated circuit can include multiple analog-to-digital converters (ADCs) sharing a reference voltage that can be perturbed by a capacitor array of a digital-to-analog converter (DAC) sampling the reference voltage, which can limit conversion accuracy. Synchronizing every bit trial across the ADCs can improve accuracy but can slow the conversion. Synchronizing a subset of at least one, but fewer than N, bit trials across ADCs can help obtain both speed and robustness. This selected subset can include bit trials corresponding to pro-defined critical events, such as those events for which a stable reference voltage node is particularly desirable.

Abstract: Disclosed herein are microphone arrays for directional reception, along with related system, devices, and techniques. For example, a four-microphone array for directional signal reception may include first, second, and third microphones arranged such that projections of the first, second, and third microphones in a plane provide corners of a triangle in the plane. In some embodiments, a fourth microphone may be arranged such that a projection of the fourth microphone in the plane is disposed in an interior of the triangle. In other embodiments, the fourth microphone may be arranged such that the projection of the fourth microphone in the plane is disposed outside the interior of the triangle, and a distance between the first microphone and the second microphone is different from a distance between the first microphone and the third microphone.

Abstract: Apparatus for detecting a presence of a target in a room is disclosed. The apparatus includes a motion-sensitive passive infrared (PIR) sensor, an imaging sensor, and a control unit. The PIR sensor is adapted to provide a motion signal, while the imaging sensor is adapted to generate at least a first image and a second image. The control unit is adapted to provide either a first signal or a second signal, depending on the strength of the motion and a comparison of the first and second images, where the first signal indicates a presence of the target and the second signal indicates an absence of the target. Also disclosed are a system for controlling lighting in a room, a method for detecting a presence of a target in a room, and a corresponding use of an apparatus for controlling lighting in a room.

Abstract: Sound waves cause pressure changes in the air, and the pressure changes cause changes in the dielectric constant of air. Capacitive sensor measurements indicative of the changes in the dielectric constant of air can be processed to extract features associated with sound waves in the air. The features can include sound pressure levels represented and recordable as audio samples. Furthermore, the features can help identify types of sounds, determine direction of travel of the sound waves, and/or determine the source location of the audio. Instead of relying on movement of a mechanical member to transduce sound waves through a port into an electrical signal, an improved microphone uses capacitive sensing to directly sample and sense static pressure as well as dynamic pressure or pressure changes in the air to derive audio samples. The resulting microphone avoids disadvantages of the conventional microphone having the moving mechanical member and port.

Abstract: An apparatus comprises a delta-sigma analog-to-digital converter (ADC) and baseband processing circuitry. The delta-sigma ADC includes a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC; a main quantizer circuit including a main ADC circuit and a main digital-to-analog converter (DAC) circuit, wherein an input to the main ADC circuit is operatively coupled to the plurality of integrator stages; and a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC. The baseband circuitry is configured to activate the first feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.