Abstract: The present invention relates to a switched mode voltage regulator circuit comprising a regulation loop coupled between the output voltage of the regulator and a switch driver. The regulation loop comprising an error signal generator supplying a digital error signal representative of a voltage difference between the output voltage and a reference voltage. The regulation loop further comprises a linear digital filter and a non-linear digital filter both coupled for receipt of the digital error signal and a digital summer coupled for receipt of linearly and non-linearly filtered digital error signals to provide a combined digital error signal. A digital pulse modulator is configured to generate the pulse width or pulse density modulated driver control signal in accordance with the combined digital error signal.

Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.

Abstract: Apparatus and methods to increase the range of a signal processing circuit. A system uses floating bias circuits coupled to a signal processing circuit to increase the range of power supplies that can be used with the signal processing circuit, while maintaining the components of the signal processing circuit within a breakdown voltage threshold. As the voltage level of the data signal varies, the voltage level of the floating bias circuits varies as well.

Abstract: In an example embodiment, a circuit is provided that includes a pre-fetch unit configured to pre-fetch instructions and data from a flash used by a microprocessor and decode the instructions and data without storing and accessing an address history, wherein the pre-fetcher is aware of the microprocessor's instruction set and performs parallel direct decode of each instruction accessed from the flash. In an example embodiment, method for pre-fetching instructions from a flash to a microprocessor is provided that includes reading a line of program code from the flash, assigning the instructions or data in the line to a thread in a hopper maintained in a cache, decoding the instructions to detect branches, and initiating a fetch from the flash if the target instruction is not found in one of the hoppers in the cache, building and maintaining predicted threads of instructions most likely to be executed by the microprocessor.

Abstract: An embodiment of a digital-to-analog converter circuit includes a resistor network connected to an output node, a switch network having a first plurality of switches connecting the resistor network to a first circuit node and a second plurality of switches connecting the resistor network to a second circuit node, a voltage reference to supply a reference voltage to the first circuit node, and a current generator connected to the first circuit node and the second circuit node, to generate a compensation current, draw the compensation current from the first circuit node, and supply the compensation current to the second circuit node. The current generator can generate the compensation current as a function of a current or a voltage of a component of the voltage reference or as a function of an analog output voltage produced at the output node.

Abstract: Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.

Abstract: Apparatus and methods are disclosed related to low-voltage radio transmitters with high spectral purity. One such apparatus includes a baseband path with a predistortion stage, a programmable filter, and an upconverter core. In an embodiment, the programmable filter is placed between the predistortion stage and the upconverter core. In an embodiment, the programmable filter is configured by a controller to reject out-of-band noise introduced at the predistortion stage or earlier.

Abstract: An electrical circuit includes a photodiode that receives a light signal from a light source and generates a photocurrent signal, a trans-impedance amplifier that amplifies the photocurrent signal and generates a low noise signal, and a high pass filter that converts the low noise signal into an alternating current (AC) signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude. The electrical circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The electrical circuit further includes at least one analog-to-digital converter that receives the positive and negative integrated values.

Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (??) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

Abstract: A semiconductor circuit comprises a digital circuit portion, which in turn comprises a combinatorial logic block. The semiconductor circuit comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion such as register addresses and/or memory addresses. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion through the scan chain involves writing bit values to inputs of the individually addressable scan control registers and reading bit values from at least one output of an individually addressable scan control register.

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract: Embodiments of the present invention may provide string DAC architecture with multiple stages for efficient resolution extension. A first stage may include an impedance string (e.g., resistor string). A second stage may include a switch network with each switch having more than two states (impedance values). A third stage may include a string DAC with an impedance string with a set of corresponding switches. In multi-channel embodiments, multiple second and third stages may be provided for each channel while sharing the same first stage (i.e., impedance string). Each second stage switch networks may be controlled based on the relationship between the different channels such as MSB values. Thus, the second stage switch networks may provide different impedance values to compensate for loading effects in multi-channel, multi-stage string DAC designs.

Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.

Abstract: An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. The integrator system may receive analog and digital input signals.

Abstract: Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block. The signal channels are configured to receive a plurality of input signals and to generate a plurality of output signals, and each of the signal channels has a substantially similar circuit topology. The first proxy channel has a substantially similar circuit topology as the plurality of signal channels, and includes an output that can vary in relation to a common-mode error of the signal channels. The subtraction block is configured to generate a plurality of modified output signals by using the output of the first proxy channel to reduce the common-mode error of the plurality of output signal channels.

Abstract: Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation.

Abstract: An embodiment of a digital-to-analog converter circuit includes a resistor network connected to an output node, a switch network having a first plurality of switches connecting the resistor network to a first circuit node and a second plurality of switches connecting the resistor network to a second circuit node, a voltage reference to supply a reference voltage to the first circuit node, and a current generator connected to the first circuit node and the second circuit node, to generate a compensation current, draw the compensation current from the first circuit node, and supply the compensation current to the second circuit node. The current generator can generate the compensation current as a function of a current or a voltage of a component of the voltage reference or as a function of an analog output voltage produced at the output node.

Abstract: A method and apparatus for automatic resonance detection is disclosed for a motor-driven mechanical system such as a voice coil motor (VCM) in which a resonance detector and driver are provided. The automatic resonance detector is implemented on the same integrated circuit as the driver, and dynamically determines the natural resonant frequency of the VCM driven by the driver. The resonant frequency is determined by measuring the back electromotive force (BEMF) of the VCM, detecting the slope of the BEMF signal, and determining the resonant frequency from the slope of the BEMF signal.

Abstract: In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Abstract: In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal.