Abstract: An FFT operation is performed by dividing n time-domain input points into a plurality of groups of m points, performing a plurality of constant-geometry butterfly operations on each of the groups of m points, and finally performing at least one in-place butterfly operation on the group of n points.

Abstract: In an example, there is disclosed a multiple-input analog-to-digital converter configured to receive a plurality of analog inputs and to output one or more digital outputs. In one embodiment, two input analog signals are received. The two analog signals may be mixed in a combiner, which provides them to a pipeline ADC. In another embodiment, the combiner may time multiplex the two analog input signals and provide two separate outputs signals. Advantageously, the multiple-input ADC of the present Specification may be realized with a single ADC pipeline.

Abstract: Various methods and systems are provided to control a probe moving towards fluid held in a container. The probe is moved towards the fluid to take a sample of the fluid in the container. To take a sample, probe is actuated to hit the fluid surface and to pass the fluid surface by a predetermined distance. Capacitive sensing which incorporates the probe itself is used to support an approach engine for controlling the motion of the probe. The approach engine determines the speed of the probe based on capacitance measurements, and in some cases based on position information of the probe. The approach engine ensures the probe hits the surface of the fluid in the container in order to take a sample while ensuring the probe does not hit the bottom of the container.

Abstract: Cross-talk sensitivity in an xy-axis shell-type gyroscope can be rejected or reduced by operating the gyroscope with a single in-plane flexural or bulk resonance mode and sensing two out-of-plane degenerate or non-degenerate resonance modes resulting from rotations about two axes in the plane of the resonator. Mode matching in an xy-axis shell-type gyroscope can be achieved by configuring the resonator (e.g., size, shape, thickness) to match the in-plane and out-of-plane resonance frequencies for the drive and sense modes of interest.

Abstract: Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements.

Abstract: A circuit may include a splitter, a controller, and a termination. The splitter may generate, based upon input signals, a plurality of output signals, wherein at least one of the input signals is in more than one different modes at different times and the output signals comprise a first set of the output signals generated based upon comparison of pairs of signals of the first set against each other and a second set of the output signals generated based upon comparison of each signal of the second set to a predetermined threshold voltage. The controller may determine, based upon the second set of the output signals, whether the input signals are in the one of the more than one different modes to generate one or more control signals. The termination may connect loads to each of the input lines, based upon the one or more control signals.

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract: A system and method provide for an adaptive median filter with edge protection and four line buffers to remove the impulse noise for a Bayer pattern image. The system and method separates the Bayer pattern image data into different channels by color and applies the adaptive median filter to remove the impulse noise on each channel. The adaptive median filter has five threshold values that may be modified to achieve different light condition response based on the detected noise level of the image. Thus, proper threshold values with better brightness response to the input pixels may be applied and impulse noise may be suppressed effectively, while preserving image details.

Abstract: A charge pump cell, comprising: an input node; an output node; Q channels, where Q is an integer greater than one, and where at least two of the channels comprise: a capacitor; a unidirectional current flow device; an output diode; and a channel drive signal node; and wherein a first current flow node of the unidirectional current flow device is connected to a first node of the capacitor at a channel node, a second node of the capacitor is connected to the channel drive signal node, a second current flow node of the unidirectional current flow device is connected to the input node, and the output diode is connected between the channel node and the output node

Abstract: Various embodiments provide systems and methods that allow a LIDAR system to sense nearby objects with relatively low-cost elements, and fewer elements than traditional LIDAR systems by sampling an infrared pulse at a high sample rate and storing the samples in the analog domain. The samples may then be digitized at a rate slower than the sample rate.

Abstract: An amplifier includes a fault protection control circuit biased from the signal pin and a fault protection circuit including a first PMOS transistor and a second PMOS transistor. The sources and bodies of the first and second PMOS transistors can be connected to one another, the drain of the first PMOS transistor can be connected to the amplifier's output, and the drain of the second PMOS transistor can be connected to a signal pin. During normal operating conditions, the fault protection control circuit can turn on the first and second PMOS transistors. However, the fault protection control circuit can turn off the first PMOS transistor and turn on the second PMOS transistor when an overvoltage condition is detected, and can turn on the first PMOS transistor and turn off the second PMOS transistor when an undervoltage condition is detected, even when the integrated circuit is unpowered.

Abstract: A voltage monitor comprising a first capacitive potential divider for presenting an attenuated representation of an input voltage to a comparator.

Abstract: A miniature loudspeaker may include a driver module with a flexible carrier having a proximal portion arranged within the perimeter of the frame and a distal portion arranged outside the perimeter of the frame, the flexible carrier carrying an output amplifier. The flexible carrier may be provided with electrically conductive traces connecting an amplifier input with input contact pads placed on the distal portion. The flexible carrier may be provided with electrically conductive traces connecting an amplifier output with output contact pads placed at the proximal portion. The output amplifier may be arranged on the proximal portion of the flexible carrier within the perimeter of the frame. The proximal portion of the flexible carrier may be rigidly attached to the static part. The output contact pads may be connected with the voice coil through flexible lead wires.

Abstract: The present disclosure provides for split-path data acquisition chains and associated signal processing methods. An exemplary integrated circuit for providing a split-path data acquisition signal chain includes an input terminal for receiving an analog signal; an output terminal for outputting a digital signal; and at least two frequency circuit paths coupled with the input terminal and the output terminal, wherein the at least two frequency circuit paths are configured to process different frequency components of the analog signal and recombine the processed, different frequency components, thereby providing the digital signal.

Abstract: An adaptive dead time (ADT) control scheme for use with a switch mode power converter having a full bridge with synchronous rectifiers topology. A controller which implements the control scheme includes an input circuit arranged to receive a signal representative of the converter's output voltage, and an output circuit arranged to operate the converter's switching elements and synchronous rectifiers to produce a desired output voltage. The controller is further arranged such that the converter's “dead time” is adaptively varied in an inverse relationship to the magnitude of the load current. In a preferred embodiment, the signals used to operate the synchronous rectifiers are PWM signals, and the controller adaptively varies the dead time in a linear inverse relationship to the magnitude of the load current by modulating the rising and falling edges of the signals used to operate the synchronous rectifiers.

Abstract: In a multi transmitter-receiver system, transmitter noise cancellation may be applied selectively for certain transmitters by exploiting asymmetries of the system. Hence, observation receiver(s) numbering less than the number of transmitters may be provided saving space and cost. Each observation receiver may selectively couple to a transmitter path and estimate the leakage noise from that transmitter. Based on the estimated leakage noise, noise cancellation may be applied to corresponding receiver path(s). Selection of the transmitters for leakage estimation may be based on system conditions at that time, which may be known to the system or may be estimated dynamically.

Abstract: This application discusses, among other things apparatus and methods for a voltage boost circuit. In an example, a voltage boost circuit can include first and second inverters, sharing a first supply node, and sharing a second supply node, a first charge transfer capacitor, configured to couple a first clock signal to the first inverter output, a second charge transfer capacitor, configured to couple a second clock signal to the second inverter output, the second clock signal being out-of-phase with the first clock signal, a first gate drive capacitor, configured to couple the first clock signal to the second inverter input, and a second gate drive capacitor, configured to couple the second clock signal to the first inverter input.

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. A control loop is provided to control the Ron of the switching network and provide code dependent control of switches in a DAC switching network.

Abstract: A method for balancing an electrical parameter (e.g, a current or a voltage) between phases in a multi-phase interleaved circuit includes sensing the electrical parameter, demultiplexing the electrical parameter in accordance with a phase-select signal, sampling the demultiplexed components into a plurality of digital signals, generating an error signal based on a difference between the digital signals, and modulating the phase-select signal, as applied to the phases, in accordance with the error signal.

Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.