Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Abstract: A method and system to inhibit the switching of a current mode switching converter having high and low side switching elements coupled to an output inductor, the other end of which is coupled to an output node, and operated with respective modulated switching signals to regulate an output voltage Vout produced at the node. A current IC that varies with the difference between a reference voltage and a voltage proportional to Vout is compared with and a current IDETECT—PEAK which varies with the current conducted by the high side switching element; the result of the comparison of IC and IDETECT—PEAK is used to control the regulation of Vout during normal operation. Current IC is also compared with a current IDETECT—VALLEY which varies with the current conducted by the low side switching element. When IDETECT—VALLEY>IC, a ‘skip mode’ is triggered during which the switching signals are inhibited.

Abstract: In one aspect, this disclosure relates to a method of controlling current output from a switching regulator to a load via an inductor. Inductor current information can be sampled at a peak level, such as just before a transistor configured to cause current to flow through the inductor is turned off. The sampled inductor current can be compared with a reference current, and a current limit threshold can be adjusted based on the comparison. The output current of the switching regulator can be controlled based on a comparison of the current limit threshold with an indicator of current flowing through the inductor. This method can accurately and efficiently limit current in a switching regulator.

Abstract: A MEMS sensor includes a micro-electromechanical structure, a detection circuit, and a self-test circuit to test the health of the MEMS sensor during runtime operations. The self-test circuit is configured to inject into the micro-electromechanical structure a plurality of injected test signals that are broad-band frequency-varying frequency signals, which are based on spread spectrum based modulation. The injected test signals may a magnitude that is below an observable threshold of the sensor signal as well as a test-signal bandwidth that overlaps with a substantial portion of the sensor bandwidth, including the stimulus of interest.

Abstract: Apparatus and methods for current sensing in switching regulators are provided. In certain implementations, a switching regulator includes a switch transistor, a replica transistor, a current source, a sense resistor, and a current sensing circuit. The drain and gate of the switch transistor can be electrically connected to the drain and gate of the replica transistor, respectively. Additionally, the current sensing circuit can control the voltage of the source of the replica transistor based on the polarity of a current through the switch transistor to generate an output current that changes in response to the switch transistor's current. The sense resistor can receive an offset current from the first current source and the output current from the current sensing circuit such that the voltage across the sense resistor changes in relation to the current through the switch transistor.

Abstract: A method of forming an insulating structure, comprising forming an insulating region comprising at least one electrical or electronic component or part thereof embedded within the insulating region, and forming a surface structure in a surface of the insulating region.

Abstract: A single-axis tilt-mode microelectromechanical accelerometer structure. The structure includes a substrate having a top surface defined by a first end and a second end. Coupled to the substrate is a first asymmetrically-shaped mass suspended above the substrate pivotable about a first pivot point on the substrate between the first end and the second end and a second asymmetrically-shaped mass suspended above the substrate pivotable about a second pivot point on the substrate between the first end and the second end. The structure also includes a first set of electrodes positioned on the substrate and below the first asymmetrically-shaped mass and a second set of electrodes positioned on the substrate and below the second asymmetrically-shaped mass.

Abstract: Advanced TDM daisy-chain configurations utilize data transmission over a frame sync signal path with feedback to allow for communication between the master device and slave devices and/or between individual slave devices while maintaining a simple TDM communication interface. In certain daisy-chain configurations, the feedback path returns to the frame sync signal path between the master device and the first slave device, which allows for transmission of data from the last slave device to the master device and/or to the first slave device. In other daisy-chain configurations, the feedback path returns to the frame sync signal path between the first slave device and the second slave device, which allows for transmission of data from the last slave device to the first slave device (which may transfer data to the master device, e.g., over separate command and/or data lines) and/or to the first slave device.

Abstract: A microphone circuit assembly for an external application processor, such as a programmable Digital Signal Processor, may include a microphone preamplifier and analog-to-digital converter to generate microphone signal samples at a first predetermined sample rate. A speech feature extractor is configured for receipt and processing of predetermined blocks of the microphone signal samples to extract speech feature vectors representing speech features of the microphone signal samples. The microphone circuit assembly may include a speech vocabulary comprising a target word or target phrase of human speech encoded as a set of target feature vectors and a decision circuit is configured to compare the speech feature vectors generated by the speech feature extractor with the target feature vectors to detect the target speech word or phrase.

Abstract: A system for processor wake-up based on sensor data includes an audio buffer, an envelope buffer, and a processor. The audio buffer is configured to store a first data from a sensor. The first data is generated according to a first sampling rate. The envelope buffer is configured to store a second data, which is derived from the first data according to a second sampling rate, which is less than the first sampling rate. The processor is configured to wake up periodically from an idle state and read the second data from the envelope buffer. If the second data indicates an activity, the processor is configured to read the first data from the audio buffer. If the second data does not indicate an activity, the processor is configured to return to the idle state.

Abstract: A multi-channel isolation system has N+1 isolators for N channels of communication data. N of the isolators may transfer data signals across an isolation barrier, one for each of the N channels of data. An N+1st isolator transfers refresh signals representing state of the data signals on the N isolators. Receiver circuitry, therefore, may receive signals from the N isolation channels without risk for collision with refresh signals. If reception of the refresh signals becomes necessary, circuitry on a receive side of the isolator may switch over to the N+1st receive path to output state data contained in the refresh signals.

Abstract: A method and corresponding circuits for operating a parallel DMOS switch that includes a pair of P-type DMOS devices connected in series with each other and in parallel with a pair of N-type DMOS devices connected in series with each other. The method and circuits involve turning the switch on by applying gate signals to the DMOS device pairs which are generated using at least one source voltage of a DMOS device pair. The switch is turned off by setting the gate signals equal to the respective source voltages of the DMOS device pairs.

Abstract: A switching device for heterojunction integrated circuits is disclosed. According to one aspect, the switching device is configured to protect a circuit from an electro-static discharge (ESD) event. The switching device includes a second base contact region that is configured to be electrically floating, a first base contact region and a collector contact region that are coupled to a first input terminal of the switching device, and an emitter contact region that is coupled to a second input terminal of the switching device. Due in part to capacitive coupling between the first base contact region and the second base contact region, the switching device exhibits a low transient trigger voltage and a fast response to ESD events. Further, the switching device exhibits a high DC trigger voltage (for example, greater than 20V), while maintaining relatively low leakage current during operation (for example, less than about 0.5 ?A at 20V DC.

Abstract: A compact sensor module and methods for forming the same are disclosed herein. In some embodiments, a sensor die is mounted on a sensor substrate. A processor die can be mounted on a flexible processor substrate. In some arrangements, a thermally insulating stiffener can be disposed between the sensor substrate and the flexible processor substrate. At least one end portion of the flexible processor substrate can be bent around an edge of the stiffener to electrically couple to the sensor substrate.

Abstract: A charge pump system and method that may provide large supply voltages and currents with reduced ripple voltage at reduced ripple frequency. The charge pump system may include an array of charge pumps and a delay pipeline. The array of charge pumps may include a plurality of charge pumps. The delay pipeline may include a plurality of delay elements. The delay elements may respond to a global trigger signal to output a trigger signal to the array of charge pumps. Respective charge pumps may fire in response to the trigger signal.

Abstract: A delay locked loop (DLL) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (PFD) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal.

Abstract: In a data processing system, a method for implementing a factor graph having variable nodes and function nodes connected to each other by edges includes implementing a first function node and a on a first computer system, the first computer system being in network communication with a second computer system; establishing a network connection to each of a plurality of processing systems; receiving, at the first function node, soft data from a variable node implemented on one of the processing systems, the soft data including an estimate of a value and information representative of an extent to which the estimate is believed to correspond to a correct value; and transmitting, from the first function node to the one of the processing systems, soft data representing an updated estimate of the value.

Abstract: A negative current protection system for a low side switching converter FET, for use with a switching converter arranged to operate high and low side FETs connected to an output inductor to produce an output voltage. The negative current protection system comprises a current sensing circuit which produces an output Vcs that varies with the current in the high side FET, a negative current threshold generator which produces a threshold signal ?Ith which represents the maximum negative current to which the low side FET is to be subjected, and a comparison circuit arranged to compare the valley portion of Vcs and ?Ith and to set a flag if Vcs<?Ith at a predetermined time in the switching cycle—typically after the converter's blanking time. When the flag is set, the system preferably responds by adjusting the operation of the switching FETs to reduce the negative current.

Abstract: An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer. The p-type thermoelectric elements and the n-type thermoelectric elements may be connected in series while alternating between the p-type and the n-type thermoelectric elements.

Abstract: One embodiment relates to a method of compensating for crystal frequency variation over temperature. An example method includes obtaining an indication of temperature, computing a temperature compensation value based on the indication of temperature and a piecewise linear temperature compensation approximation, and compensating for a temperature offset in a crystal reference signal by adjusting a division ratio of a fractional divider in a phase-locked loop. The piecewise linear temperature compensation approximation can represent an approximation of frequency error in a crystal reference signal originating from a crystal over temperature. The piecewise linear temperature compensation approximation can be, for example, a linear approximation, a quadratic approximation, or a cubic approximation.