Abstract: The present invention may provide a system including a controller and a plurality of integrated circuits. The controller may control synchronization operations of the system, the controller may include a master timing counter and a controller data interface. Each integrated circuit may include a timing counter and an IC data interface. Further, each integrated circuit may synchronize its respective timing counter based on synchronization command received from the controller via the data interfaces. Hence, the system may provide synchronization between the controller and the integrated circuits without an extraneous designated pin(s) for a designated common time-based signal.

Abstract: Aspects of the present invention provide apparatuses and methods to provide significant gain enhancement for a cascode structure for a differential amplifier. The cascode structure of the differential amplifier can include first and second pairs of output transistors. The second pair of output transistors can be configured to approximately cancel modulation effects of the first pair of output transistors induced by changes in a differential output of differential amplifier, thereby resulting in conditions for providing enhanced gain.

Abstract: An isolator system is disclosed in which a pair of circuit systems is separated by an isolation barrier but engage in mutual communication by an isolator device that bridges the isolation barrier. A first circuit system may include a measurement system generating measurement data and status monitor generating status data. The first circuit system also may include a communication system that multiplexes the measurement data and the status data for transmission across a common isolator device. In this manner, the number of isolator devices may be reduced over conventional designs.

Abstract: Embodiments of the present invention may provide a system with a first and second circuit system separated by an electrical isolation barrier but provided in communication by at least one isolator device that bridges the isolation barrier. The first circuit system may include a communication system to transmit data across a common isolator device as a series of pulses, and the second circuit system may receive the series of pulses corresponding to the data. The second circuit system may include a detector coupled to the common isolator device to detect the received pulses, a oneshot to frame the received pulse(s), and a controller to reconstruct the data based on accumulated framed pulse(s). Therefore, noise induced spurious pulses outside the oneshot intervals may be ignored by the second circuit system providing improved noise immunity.

Abstract: A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.

Abstract: Metal oxide semiconductor (MOS) protection circuits and methods of forming the same are disclosed. In one embodiment, an integrated circuit includes a pad, a p-type MOS (PMOS) transistor, and first and second n-type MOS (NMOS) transistors. The first NMOS transistor includes a drain, a source and a gate electrically connected to the pad, a first supply voltage, and a drain of the PMOS transistor, respectively. The second NMOS transistor includes a gate, a drain, and a source electrically connected to a bias node, a second supply voltage, and a source of the PMOS transistor, respectively. The source of the second NMOS transistor is further electrically connected to a body of the PMOS transistor so as to prevent a current flowing from the drain of the PMOS transistor to the second supply voltage through the body of PMOS transistor when a transient signal event is received on the pad.

Abstract: Techniques to reduce correlated errors in a multi-channel sampling system. A plurality of clock signals may be generated from a master clock signal, each with edges offset from each other. The offset clock signals may be distributed to a plurality of sampling devices. Each sampling device may capture a respective input signal according to its offset clock. In this manner, the sampling units may sample their inputs signals over a distributed window of time rather than sampling in response to a common clock edge. By distributing the switching operations performed by the sampling units, noise effects are likely to be reduced.

Abstract: Apparatus and methods for frequency compensation of an amplifier are provided. In one embodiment, an integrated circuit (IC) includes an amplifier configured to amplify an input signal to generate an output signal. The IC further includes an output pad configured to receive an output signal from the amplifier and a control pad for controlling the closed-loop bandwidth of the amplifier. A compensation capacitor is electrically connected between an input of the inverting amplification block and an output of the inverting amplification block, and a switchable capacitor is electrically connected between the input of the inverting amplification block and the control pad. The control pad can be electrically connected to a DC voltage source or to the output pad to control the amplifier's closed-loop bandwidth.

Abstract: A digital sine wave may be converted to an analog signal at a digital to analog converter (DAC). The converted analog signal may be supplied to a device and an analog return signal from the device may be passed through a relaxed anti-aliasing filter and converted to digital code words at an analog to digital converter (ADC). An impedance may be calculated from the results of a Fourier analysis of the digital code words. The ADC and DAC clock frequencies may be asynchronous, independently variable, and have a greatest common factor of 1. The clock frequencies of the ADC and/or DAC may be adjusted to change a location of images in the ADC spectrum. By using these different, adjustable clock frequencies for the ADC and the DAC, an analog signal may have increased aliasing without introducing signal errors at a frequency of interest.

Abstract: Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer can include a programmable gain amplifier (PGA) block which includes an input node configured to receive the input signal; an output node; and a programmable gain amplifier (PGA). The PGA amplifies the input signal with an adjustable gain. The PGA block also includes a gain control block having an input electrically coupled to the input node. The gain control block is configured to adjust the gain of the PGA at least partly in response to the input signal from the input node such that the PGA generates an output signal with a substantially constant amplitude envelope to the output node.

Abstract: An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.

Abstract: An inertial sensor includes driving piezoelectric transducers for enabling an oscillation of a resonator, sensing piezoelectric transducers for enabling a detection of a movement of the inertial sensor, and piezoelectric compensating elements substantially equidistantly among the driving and the sensing piezoelectric transducers, wherein the compensating elements and the resonator form corresponding capacitors having capacitive gaps, and wherein, during the oscillation of the resonator, changes in electrostatic charges stored in the capacitors are measured with the compensating elements and are modified so as to modify the oscillation of the resonator.

Abstract: A method for altering a resistance of a resistor including trimming the resistor using a first type of trim approach to increase a resistance measurement of the resistor to above a target resistance value, and iteratively trimming the resistor using a second type of trim approach until a power coefficient of resistance (PCR) or temperature coefficient of resistance (TCR) measurement of the resistor is substantially close to zero.

Abstract: A MEMS device includes a substrate, a mass having a first and second set of elongated mass fingers extending from the mass, and a support structure supporting the mass on the substrate. The support structure may include at least one anchor and a plurality of springs that allow movement of the mass relative to the substrate. The MEMS device may also include a first set of sensing fingers for sensing movement of the first set of mass fingers relative to the first set of sensing fingers, and a second set of sensing figures for sensing movement of the second set of mass fingers relative to the second set of sensing fingers. The first and second sets of sensing fingers may have different size finger gaps between the sensing fingers and the respective mass fingers.

Abstract: An inertial sensor includes driving piezoelectric transducers for enabling an oscillation of a resonator, sensing piezoelectric transducers for enabling a detection of a movement of the inertial sensor, and piezoelectric compensating elements substantially equidistantly among the driving and the sensing piezoelectric transducers, wherein the compensating elements and the resonator form corresponding capacitors having capacitive gaps, and wherein, during the oscillation of the resonator, changes in electrostatic charges stored in the capacitors are measured with the compensating elements and are modified so as to modify the oscillation of the resonator.

Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a substrate includes an n-well and a p-well adjacent the n-well. An n-type active area and a p-type active area are disposed in the n-well. The p-type active area, the n-well, and the p-well are configured to operate as an emitter, a base, and a collector of an PNP bipolar transistor, respectively, and the p-type active area surrounds at least a portion of the n-type active area so as to aid in recombining carriers injected into the n-well from the p-well before the carriers reach the n-type active area. The n-well and the p-well are configured to operate as a breakdown diode, and a punch-through breakdown voltage between the n-well and the p-well is lower than or equal to about a breakdown voltage between the p-type active area and the n-well.

Abstract: A reference circuit for use with a charge redistribution analog to digital converter, having a capacitor array, the reference circuit comprising: an input for receiving a signal; an output for supplying a reference voltage to at least one capacitor of the charge redistribution capacitor array; a storage capacitor for storing the reference voltage; a voltage modification circuit for comparing the reference voltage stored on the storage capacitor with the reference signal, and based on the comparison to supply a correction so as to reduce a difference between the reference voltage and the reference signal, the correction being applied during a correction phase; and a first switch for selectively connecting the storage capacitor to the input during an acquisition phase.

Abstract: A computed tomography detector module can include a detector element, a frame, and a converter element. The detector element can be configured to detect electromagnetic radiation at a detection plane and output one or more analog detection signals. The frame can connect to the detector element and include a shield portion, parallel to the detection plane, configured to at least partially block X-rays. The converter element can include a substrate having connector and component substrate portions, the connector substrate portion thicker in a direction perpendicular to the detection plane than the component substrate portion and configured to extend through an aperture of the frame, the component substrate portion having at least one substrate surface parallel to the detection plane with one or more electrical components attached thereto.

Abstract: Apparatus and methods for adaptive level shifting are provided. In one embodiment, a method of level shifting in an adaptive level shifter (ALS) is provided. The technique includes charging a first capacitor and a second capacitor each to a voltage that is about equal to a difference between a common mode voltage of a differential input voltage signal and a reference voltage. The technique can further include inserting the first capacitor between a first input and a first output of the ALS and the second capacitor between the second input and a second output of the ALS. The technique can further include switching the first capacitor and the second capacitor such that the first capacitor is inserted between the second input and the second output and the second capacitor is inserted between the first input and the first output.

Abstract: DC-DC voltage converter structures and methods are provided that employ first and second transistors which are switched to control currents through an inductor and a capacitor to thereby provide an output voltage substantially equal to a predetermined reference voltage. Preferably included is a voltage feedback loop in which an error voltage is fed back to a loop comparator and further included is a current feedback loop that provides to the comparator a first voltage ramp whose amplitude is proportional to the amplitude of the converter's input current. The output signal of the comparator sets the duty cycles of the first and second transistors. In each converter period, the first and second transistors of the voltage converter respectively control, through the inductor, a first current with a rising slope and a second current with a falling slope. Finally, converter stability is enhanced by providing a second voltage ramp having a slope related to a fraction (e.g.